diff mbox series

phy: mediatek: mipi: mt8183: fix minimal supported frequency

Message ID 20231123110202.2025585-1-mwalle@kernel.org (mailing list archive)
State New, archived
Headers show
Series phy: mediatek: mipi: mt8183: fix minimal supported frequency | expand

Commit Message

Michael Walle Nov. 23, 2023, 11:02 a.m. UTC
The lowest supported clock frequency of the PHY is 125MHz (see also
mtk_mipi_tx_pll_enable()), but the clamping in .round_rate() has the
wrong minimal value, which will make the .enable() op return -EINVAL on
low frequencies. Fix the minimal clamping value.

Fixes: efda51a58b4a ("drm/mediatek: add mipi_tx driver for mt8183")
Signed-off-by: Michael Walle <mwalle@kernel.org>
---
 drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

AngeloGioacchino Del Regno Nov. 23, 2023, 11:22 a.m. UTC | #1
Il 23/11/23 12:02, Michael Walle ha scritto:
> The lowest supported clock frequency of the PHY is 125MHz (see also
> mtk_mipi_tx_pll_enable()), but the clamping in .round_rate() has the
> wrong minimal value, which will make the .enable() op return -EINVAL on
> low frequencies. Fix the minimal clamping value.
> 
> Fixes: efda51a58b4a ("drm/mediatek: add mipi_tx driver for mt8183")
> Signed-off-by: Michael Walle <mwalle@kernel.org>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Vinod Koul Nov. 27, 2023, 1:22 p.m. UTC | #2
On Thu, 23 Nov 2023 12:02:02 +0100, Michael Walle wrote:
> The lowest supported clock frequency of the PHY is 125MHz (see also
> mtk_mipi_tx_pll_enable()), but the clamping in .round_rate() has the
> wrong minimal value, which will make the .enable() op return -EINVAL on
> low frequencies. Fix the minimal clamping value.
> 
> 

Applied, thanks!

[1/1] phy: mediatek: mipi: mt8183: fix minimal supported frequency
      commit: 06f76e464ac81c6915430b7155769ea4ef16efe4

Best regards,
diff mbox series

Patch

diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
index f021ec5a70e5..553725e1269c 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
@@ -100,7 +100,7 @@  static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
 static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 				       unsigned long *prate)
 {
-	return clamp_val(rate, 50000000, 1600000000);
+	return clamp_val(rate, 125000000, 1600000000);
 }
 
 static const struct clk_ops mtk_mipi_tx_pll_ops = {