Message ID | 20231126232746.264302-3-emil.renner.berthing@canonical.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Conor Dooley |
Headers | show |
Series | Add JH7100 errata and update device tree | expand |
On Mon, Nov 27, 2023 at 12:27:40AM +0100, Emil Renner Berthing wrote: > From: Geert Uytterhoeven <geert@linux-m68k.org> > > To improve human readability and enable automatic validation, the tuples > in the various properties containing interrupt specifiers should be > grouped. > > Fix this by grouping the tuples of "interrupts-extended" properties > using angle brackets. > > Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> This one is missing your signoff Emil.
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index e68cafe7545f..a40a8544b860 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -149,15 +149,15 @@ soc { clint: clint@2000000 { compatible = "starfive,jh7100-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0x10000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>; }; plic: interrupt-controller@c000000 { compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; - interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9 - &cpu1_intc 11 &cpu1_intc 9>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>; interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>;