| Message ID | 20231129060043.368874-2-jeeheng.sia@starfivetech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Initial device tree support for StarFive JH8100 SoC | expand |
On Wed, Nov 29, 2023 at 02:00:38PM +0800, Sia Jee Heng wrote: > Add new compatible strings for Dubhe-80 and Dubhe-90. These are > RISC-V cpu core from StarFive Technology and are used in StarFive > JH8100 SoC. > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index f392e367d673..493972b29a22 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -48,6 +48,8 @@ properties: > - thead,c906 > - thead,c910 > - thead,c920 > + - starfive,dubhe-80 > + - starfive,dubhe-90 s goes before t. Cheers, Conor. > - const: riscv > - items: > - enum: > -- > 2.34.1 >
> -----Original Message----- > From: Conor Dooley <conor@kernel.org> > Sent: Wednesday, November 29, 2023 10:46 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com> > Cc: kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; krzk@kernel.org; conor+dt@kernel.org; > paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; daniel.lezcano@linaro.org; tglx@linutronix.de; > anup@brainfault.org; gregkh@linuxfoundation.org; jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu > <michael.zhu@starfivetech.com>; drew@beagleboard.org; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux- > kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com> > Subject: Re: [PATCH v2 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles > > On Wed, Nov 29, 2023 at 02:00:38PM +0800, Sia Jee Heng wrote: > > Add new compatible strings for Dubhe-80 and Dubhe-90. These are > > RISC-V cpu core from StarFive Technology and are used in StarFive > > JH8100 SoC. > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index f392e367d673..493972b29a22 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -48,6 +48,8 @@ properties: > > - thead,c906 > > - thead,c910 > > - thead,c920 > > + - starfive,dubhe-80 > > + - starfive,dubhe-90 > > s goes before t. Noted. Will fix it. > > Cheers, > Conor. > > > - const: riscv > > - items: > > - enum: > > -- > > 2.34.1 > >
On Thu, Nov 30, 2023 at 06:04:51AM +0000, JeeHeng Sia wrote: > > > > -----Original Message----- > > From: Conor Dooley <conor@kernel.org> > > Sent: Wednesday, November 29, 2023 10:46 PM > > To: JeeHeng Sia <jeeheng.sia@starfivetech.com> > > Cc: kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; krzk@kernel.org; conor+dt@kernel.org; > > paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; daniel.lezcano@linaro.org; tglx@linutronix.de; > > anup@brainfault.org; gregkh@linuxfoundation.org; jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu > > <michael.zhu@starfivetech.com>; drew@beagleboard.org; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux- > > kernel@vger.kernel.org; Leyfoon Tan <leyfoon.tan@starfivetech.com> > > Subject: Re: [PATCH v2 1/6] dt-bindings: riscv: Add StarFive Dubhe compatibles > > > > On Wed, Nov 29, 2023 at 02:00:38PM +0800, Sia Jee Heng wrote: > > > Add new compatible strings for Dubhe-80 and Dubhe-90. These are > > > RISC-V cpu core from StarFive Technology and are used in StarFive > > > JH8100 SoC. > > > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > > --- > > > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > index f392e367d673..493972b29a22 100644 > > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > @@ -48,6 +48,8 @@ properties: > > > - thead,c906 > > > - thead,c910 > > > - thead,c920 > > > + - starfive,dubhe-80 > > > + - starfive,dubhe-90 > > > > s goes before t. > Noted. Will fix it. With the re-order, Acked-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index f392e367d673..493972b29a22 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -48,6 +48,8 @@ properties: - thead,c906 - thead,c910 - thead,c920 + - starfive,dubhe-80 + - starfive,dubhe-90 - const: riscv - items: - enum: