| Message ID | 20231130213103.214915-1-khaled.almahallawy@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] drm/i915/dp: Use LINK_QUAL_PATTERN_* Phy test pattern names | expand |
On Fri, 2023-12-01 at 02:53 +0000, Patchwork wrote: > Patch Details > Series: series starting with [v2,1/2] drm/i915/dp: Use > LINK_QUAL_PATTERN_* Phy test pattern names > URL: https://patchwork.freedesktop.org/series/127146/ > State: failure > Details: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127146v1/index.html > CI Bug Log - changes from CI_DRM_13956 -> Patchwork_127146v1 > Summary > FAILURE > > Serious unknown changes coming with Patchwork_127146v1 absolutely > need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_127146v1, please notify your bug team ( > I915-ci-infra@lists.freedesktop.org) to allow them > to document this new failure mode, which will reduce false positives > in CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127146v1/index.html > > Participating hosts (39 -> 34) > Missing (5): fi-bsw-n3050 fi-snb-2520m bat-atsm-1 fi-pnv-d510 bat- > mtlp-8 > > Possible new issues > Here are the unknown changes that may have been introduced in > Patchwork_127146v1: > > IGT changes > Possible regressions > igt@kms_pipe_crc_basic@nonblocking-crc@pipe-b-dp-6: > bat-adlp-11: PASS -> DMESG-WARN > Known issues > Here are the changes found in Patchwork_127146v1 that come from known > issues: > This warning is not related to changes in this patch. seems this machine has MST hub connected and the payload is failing. The changes in this patch will be triggered only when we are connected to DP Scope with DPR-100. Could you please report? Thanks Khaled > IGT changes > Issues hit > igt@gem_lmem_swapping@basic: > > fi-apl-guc: NOTRUN -> SKIP (fdo#109271 / i915#4613) +3 other tests > skip > igt@kms_hdmi_inject@inject-audio: > > fi-kbl-guc: PASS -> FAIL (IGT#3) > igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-5: > > bat-adlp-11: PASS -> DMESG-FAIL (i915#6868) > igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-dp-5: > > bat-adlp-11: PASS -> FAIL (i915#9666) > igt@kms_pipe_crc_basic@read-crc-frame-sequence: > > bat-dg2-11: NOTRUN -> SKIP (i915#1845 / i915#9197) > igt@kms_pipe_crc_basic@read-crc@pipe-b-dp-6: > > bat-adlp-11: PASS -> ABORT (i915#8668) > igt@kms_pipe_crc_basic@suspend-read-crc: > > bat-rpls-1: NOTRUN -> SKIP (i915#1845) > Possible fixes > igt@core_hotunplug@unbind-rebind: > > fi-apl-guc: ABORT (i915#8213 / i915#8668) -> PASS > igt@gem_exec_suspend@basic-s3@smem: > > bat-rpls-1: ABORT (i915#7978) -> PASS > Build changes > Linux: CI_DRM_13956 -> Patchwork_127146v1 > CI-20190529: 20190529 > CI_DRM_13956: b59a0a6520764f36a79ba6b4c590e243ac6b913d @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_7612: b5c47966901ee1060bcb9d4bccdd3ccec9651ef4 @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_127146v1: b59a0a6520764f36a79ba6b4c590e243ac6b913d @ > git://anongit.freedesktop.org/gfx-ci/linux > > Linux commits > 495fc28b6019 drm/i915/dp: Add TPS4 PHY test pattern support > e49d81ed6615 drm/i915/dp: Use LINK_QUAL_PATTERN_* Phy test pattern > names
On Thu, 30 Nov 2023, Khaled Almahallawy <khaled.almahallawy@intel.com> wrote: > Starting from DP2.0 specs, DPCD 248h is renamed > LINK_QUAL_PATTERN_SELECT and it has the same values of registers > DPCD 10Bh-10Eh. > Use the PHY pattern names defined for DPCD 10Bh-10Eh in order to add > CP2520 Pattern 3 (TPS4) phy pattern support in the next > patch of this series and DP2.1 PHY patterns for future series. > > v2: rebase > > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Lee Shawn C <shawn.c.lee@intel.com> > Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 3b2482bf683f..a1e63ab5761b 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4683,27 +4683,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, > u32 pattern_val; > > switch (data->phy_pattern) { > - case DP_PHY_TEST_PATTERN_NONE: > + case DP_LINK_QUAL_PATTERN_DISABLE: > drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n"); > intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); > break; > - case DP_PHY_TEST_PATTERN_D10_2: > + case DP_LINK_QUAL_PATTERN_D10_2: > drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n"); > intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), > DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); > break; > - case DP_PHY_TEST_PATTERN_ERROR_COUNT: > + case DP_LINK_QUAL_PATTERN_ERROR_RATE: > drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n"); > intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), > DDI_DP_COMP_CTL_ENABLE | > DDI_DP_COMP_CTL_SCRAMBLED_0); > break; > - case DP_PHY_TEST_PATTERN_PRBS7: > + case DP_LINK_QUAL_PATTERN_PRBS7: > drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n"); > intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), > DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); > break; > - case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: > + case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM: > /* > * FIXME: Ideally pattern should come from DPCD 0x250. As > * current firmware of DPR-100 could not set it, so hardcoding > @@ -4721,7 +4721,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, > DDI_DP_COMP_CTL_ENABLE | > DDI_DP_COMP_CTL_CUSTOM80); > break; > - case DP_PHY_TEST_PATTERN_CP2520: > + case DP_LINK_QUAL_PATTERN_CP2520_PAT_1: > /* > * FIXME: Ideally pattern should come from DPCD 0x24A. As > * current firmware of DPR-100 could not set it, so hardcoding
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 3b2482bf683f..a1e63ab5761b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4683,27 +4683,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, u32 pattern_val; switch (data->phy_pattern) { - case DP_PHY_TEST_PATTERN_NONE: + case DP_LINK_QUAL_PATTERN_DISABLE: drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n"); intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); break; - case DP_PHY_TEST_PATTERN_D10_2: + case DP_LINK_QUAL_PATTERN_D10_2: drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n"); intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); break; - case DP_PHY_TEST_PATTERN_ERROR_COUNT: + case DP_LINK_QUAL_PATTERN_ERROR_RATE: drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n"); intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_SCRAMBLED_0); break; - case DP_PHY_TEST_PATTERN_PRBS7: + case DP_LINK_QUAL_PATTERN_PRBS7: drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n"); intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); break; - case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: + case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM: /* * FIXME: Ideally pattern should come from DPCD 0x250. As * current firmware of DPR-100 could not set it, so hardcoding @@ -4721,7 +4721,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_LINK_QUAL_PATTERN_CP2520_PAT_1: /* * FIXME: Ideally pattern should come from DPCD 0x24A. As * current firmware of DPR-100 could not set it, so hardcoding
Starting from DP2.0 specs, DPCD 248h is renamed LINK_QUAL_PATTERN_SELECT and it has the same values of registers DPCD 10Bh-10Eh. Use the PHY pattern names defined for DPCD 10Bh-10Eh in order to add CP2520 Pattern 3 (TPS4) phy pattern support in the next patch of this series and DP2.1 PHY patterns for future series. v2: rebase Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)