| Message ID | IA1PR20MB4953EBF14C9CA436760B2A58BB85A@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | riscv: sophgo: add clock support for Sophgo CV1800 SoCs | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
Inochi Amaoto wrote: > Add missing clocks of uart node for CV1800B and CV1812H. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > --- > arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 21 ++++++++++++++++----- > 1 file changed, 16 insertions(+), 5 deletions(-) > > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > index c5642dd7cbbd..3f290a515011 100644 > --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > @@ -5,6 +5,7 @@ > */ > > #include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/clock/sophgo,cv1800.h> > > / { > #address-cells = <1>; > @@ -136,7 +137,9 @@ uart0: serial@4140000 { > compatible = "snps,dw-apb-uart"; > reg = <0x04140000 0x100>; > interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; > - clocks = <&osc>; > + clock-frequency = <25000000>; > + clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; > + clock-names = "baudclk", "apb_pclk"; > reg-shift = <2>; > reg-io-width = <4>; > status = "disabled"; Hi Inochi, When there is a proper "baudclk" defined the driver should get the rate (frequency) from that and the manually defined clock-frequency should not be needed. /Emil
> >Inochi Amaoto wrote: >> Add missing clocks of uart node for CV1800B and CV1812H. >> >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> >> --- >> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 21 ++++++++++++++++----- >> 1 file changed, 16 insertions(+), 5 deletions(-) >> >> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi >> index c5642dd7cbbd..3f290a515011 100644 >> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi >> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi >> @@ -5,6 +5,7 @@ >> */ >> >> #include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/clock/sophgo,cv1800.h> >> >> / { >> #address-cells = <1>; >> @@ -136,7 +137,9 @@ uart0: serial@4140000 { >> compatible = "snps,dw-apb-uart"; >> reg = <0x04140000 0x100>; >> interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; >> - clocks = <&osc>; >> + clock-frequency = <25000000>; >> + clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; >> + clock-names = "baudclk", "apb_pclk"; >> reg-shift = <2>; >> reg-io-width = <4>; >> status = "disabled"; > >Hi Inochi, > >When there is a proper "baudclk" defined the driver should get the rate >(frequency) from that and the manually defined clock-frequency should not be >needed. > >/Emil > OK, thanks, I will remove this.
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index c5642dd7cbbd..3f290a515011 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -5,6 +5,7 @@ */ #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/sophgo,cv1800.h> / { #address-cells = <1>; @@ -136,7 +137,9 @@ uart0: serial@4140000 { compatible = "snps,dw-apb-uart"; reg = <0x04140000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clock-frequency = <25000000>; + clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -146,7 +149,9 @@ uart1: serial@4150000 { compatible = "snps,dw-apb-uart"; reg = <0x04150000 0x100>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clock-frequency = <25000000>; + clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -156,7 +161,9 @@ uart2: serial@4160000 { compatible = "snps,dw-apb-uart"; reg = <0x04160000 0x100>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clock-frequency = <25000000>; + clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -166,7 +173,9 @@ uart3: serial@4170000 { compatible = "snps,dw-apb-uart"; reg = <0x04170000 0x100>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clock-frequency = <25000000>; + clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -176,7 +185,9 @@ uart4: serial@41c0000 { compatible = "snps,dw-apb-uart"; reg = <0x041c0000 0x100>; interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clock-frequency = <25000000>; + clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled";
Add missing clocks of uart node for CV1800B and CV1812H. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> --- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) -- 2.43.0