| Message ID | 20231207-topic-sm8650-upstream-dp-v1-3-b762c06965bb@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: qcom: sm8650: add support for DisplayPort Controller | expand |
On 12/7/23 17:37, Neil Armstrong wrote: > Declare the displayport controller present on the Qualcomm SM8650 SoC > and connected to the USB3/DP Combo PHY. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- [...] > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; What about PIXEL1 clocks? [...] > + opp-162000000 { > + opp-hz = /bits/ 64 <162000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > }; > > dispcc: clock-controller@af00000 { > @@ -2996,8 +3086,8 @@ dispcc: clock-controller@af00000 { > <&mdss_dsi0_phy 1>, > <&mdss_dsi1_phy 0>, > <&mdss_dsi1_phy 1>, > - <0>, /* dp0 */ > - <0>, > + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, > + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, > <0>, /* dp1 */ > <0>, > <0>, /* dp2 */ I noticed that this is not in line with your mdss patch [1] where there are only two DP INTFs available.. Unless all of these controllers can work using some sharing/only some at one time... Konrad [1] https://lore.kernel.org/all/20231030-topic-sm8650-upstream-mdss-v2-5-43f1887c82b8@linaro.org/
On Thu, Dec 07, 2023 at 05:37:19PM +0100, Neil Armstrong wrote: > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi [..] > + > + mdss_dp0: displayport-controller@af54000 { > + compatible = "qcom,sm8650-dp"; > + reg = <0 0xaf54000 0 0x200>, > + <0 0xaf54200 0 0x200>, > + <0 0xaf55000 0 0xc00>, > + <0 0xaf56000 0 0x400>, > + <0 0xaf57000 0 0x400>; > + > + interrupts-extended = <&mdss 12>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; > + clock-names = "core_iface", > + "core_aux", > + "ctrl_link", > + "ctrl_link_iface", > + "stream_pixel"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, > + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; > + > + operating-points-v2 = <&dp_opp_table>; > + > + power-domains = <&rpmhpd RPMHPD_MX>; Are you sure the DP TX block sits in MX? I'd expect this to be RPMHPD_MMCX, and then the PHY partially in MX... > + > + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + mdss_dp0_in: endpoint { > + remote-endpoint = <&dpu_intf0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + mdss_dp0_out: endpoint { > + }; > + }; > + }; > + > + dp_opp_table: opp-table { Is there any reason why we keep sorting 'o' after 'p' in these nodes? Regards, Bjorn
On 07/12/2023 20:47, Konrad Dybcio wrote: > > > On 12/7/23 17:37, Neil Armstrong wrote: >> Declare the displayport controller present on the Qualcomm SM8650 SoC >> and connected to the USB3/DP Combo PHY. >> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- > [...] > >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, >> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, >> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, >> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; > What about PIXEL1 clocks? PIXEL1 is not defined yet in the bindings, but available since SM8150... # grep -l PIXEL1 include/dt-bindings/ -R include/dt-bindings/clock/qcom,dispcc-sm8350.h include/dt-bindings/clock/qcom,sm8650-dispcc.h include/dt-bindings/clock/qcom,dispcc-sm8250.h include/dt-bindings/clock/qcom,sm8450-dispcc.h include/dt-bindings/clock/qcom,sm8550-dispcc.h include/dt-bindings/clock/qcom,dispcc-sdm845.h include/dt-bindings/clock/qcom,dispcc-sm8150.h include/dt-bindings/clock/qcom,dispcc-sc8280xp.h > > [...] > >> + opp-162000000 { >> + opp-hz = /bits/ 64 <162000000>; >> + required-opps = <&rpmhpd_opp_low_svs_d1>; >> + }; >> + >> + opp-270000000 { >> + opp-hz = /bits/ 64 <270000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-540000000 { >> + opp-hz = /bits/ 64 <540000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + >> + opp-810000000 { >> + opp-hz = /bits/ 64 <810000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> + }; >> }; >> dispcc: clock-controller@af00000 { >> @@ -2996,8 +3086,8 @@ dispcc: clock-controller@af00000 { >> <&mdss_dsi0_phy 1>, >> <&mdss_dsi1_phy 0>, >> <&mdss_dsi1_phy 1>, >> - <0>, /* dp0 */ >> - <0>, >> + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, >> + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, >> <0>, /* dp1 */ >> <0>, >> <0>, /* dp2 */ > I noticed that this is not in line with your mdss patch [1] > where there are only two DP INTFs available.. Unless all of > these controllers can work using some sharing/only some at > one time... So, yes there's some more eDP PHYs and MDSS Interfaces, like SM8450 and SM8550 BTW, but they are not used on the current SoC Packages, they will perhaps be used in SoC variants, but for now there's clock inputs but no physical output for those DP interfaces so they're ignored, in upstream and downstream. $ grep -l -E "DPTX[1-3]" include/dt-bindings/clock/qcom,* -R include/dt-bindings/clock/qcom,sm8450-dispcc.h include/dt-bindings/clock/qcom,sm8550-dispcc.h include/dt-bindings/clock/qcom,sm8650-dispcc.h Neil > > Konrad > > [1] https://lore.kernel.org/all/20231030-topic-sm8650-upstream-mdss-v2-5-43f1887c82b8@linaro.org/
On 08/12/2023 04:38, Bjorn Andersson wrote: > On Thu, Dec 07, 2023 at 05:37:19PM +0100, Neil Armstrong wrote: >> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > [..] >> + >> + mdss_dp0: displayport-controller@af54000 { >> + compatible = "qcom,sm8650-dp"; >> + reg = <0 0xaf54000 0 0x200>, >> + <0 0xaf54200 0 0x200>, >> + <0 0xaf55000 0 0xc00>, >> + <0 0xaf56000 0 0x400>, >> + <0 0xaf57000 0 0x400>; >> + >> + interrupts-extended = <&mdss 12>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, >> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, >> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, >> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; >> + clock-names = "core_iface", >> + "core_aux", >> + "ctrl_link", >> + "ctrl_link_iface", >> + "stream_pixel"; >> + >> + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, >> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; >> + assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, >> + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; >> + >> + operating-points-v2 = <&dp_opp_table>; >> + >> + power-domains = <&rpmhpd RPMHPD_MX>; > > Are you sure the DP TX block sits in MX? I'd expect this to be > RPMHPD_MMCX, and then the PHY partially in MX... Hmm, yeah probably, will switch to MMCX > >> + >> + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; >> + phy-names = "dp"; >> + >> + #sound-dai-cells = <0>; >> + >> + status = "disabled"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + >> + mdss_dp0_in: endpoint { >> + remote-endpoint = <&dpu_intf0_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + >> + mdss_dp0_out: endpoint { >> + }; >> + }; >> + }; >> + >> + dp_opp_table: opp-table { > > Is there any reason why we keep sorting 'o' after 'p' in these nodes? No, seems it's a copy-paste issue, will fix Thanks, Neil > > Regards, > Bjorn
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index d1442b100e79..b2a50686d419 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2781,6 +2781,14 @@ dpu_intf2_out: endpoint { remote-endpoint = <&mdss_dsi1_in>; }; }; + + port@2 { + reg = <2>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -2982,6 +2990,88 @@ mdss_dsi1_phy: phy@ae97000 { status = "disabled"; }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,sm8650-dp"; + reg = <0 0xaf54000 0 0x200>, + <0 0xaf54200 0 0x200>, + <0 0xaf55000 0 0xc00>, + <0 0xaf56000 0 0x400>, + <0 0xaf57000 0 0x400>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&dp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MX>; + + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; }; dispcc: clock-controller@af00000 { @@ -2996,8 +3086,8 @@ dispcc: clock-controller@af00000 { <&mdss_dsi0_phy 1>, <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, - <0>, /* dp0 */ - <0>, + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <0>, /* dp1 */ <0>, <0>, /* dp2 */ @@ -3054,6 +3144,32 @@ usb_dp_qmpphy: phy@88e8000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_1: usb@a6f8800 {
Declare the displayport controller present on the Qualcomm SM8650 SoC and connected to the USB3/DP Combo PHY. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 120 ++++++++++++++++++++++++++++++++++- 1 file changed, 118 insertions(+), 2 deletions(-)