[v5,1/6] riscv: Add support for kernel mode vector

Commit Message

Andy Chiu Dec. 14, 2023, 3:57 p.m. UTC

From: Greentime Hu <[e-mail]>

Add kernel_vector_begin() and kernel_vector_end() function declarations
and corresponding definitions in kernel_mode_vector.c

These are needed to wrap uses of vector in kernel mode.

Co-developed-by: Vincent Chen <[e-mail]>
Signed-off-by: Vincent Chen <[e-mail]>
Signed-off-by: Greentime Hu <[e-mail]>
Signed-off-by: Andy Chiu <[e-mail]>
---
Changelog v4:
 - Use kernel_v_flags and helpers to track vector context.
Changelog v3:
 - Reorder patch 1 to patch 3 to make use of
   {get,put}_cpu_vector_context later.
 - Export {get,put}_cpu_vector_context.
 - Save V context after disabling preemption. (Guo)
 - Fix a build fail. (Conor)
 - Remove irqs_disabled() check as it is not needed, fix styling. (Björn)
Changelog v2:
 - 's/kernel_rvv/kernel_vector' and return void in kernel_vector_begin
   (Conor)
 - export may_use_simd to include/asm/simd.h
---
 arch/riscv/include/asm/processor.h     | 15 +++-
 arch/riscv/include/asm/simd.h          | 42 ++++++++++++
 arch/riscv/include/asm/vector.h        | 21 ++++++
 arch/riscv/kernel/Makefile             |  1 +
 arch/riscv/kernel/kernel_mode_vector.c | 95 ++++++++++++++++++++++++++
 arch/riscv/kernel/process.c            |  2 +-
 6 files changed, 174 insertions(+), 2 deletions(-)
 create mode 100644 arch/riscv/include/asm/simd.h
 create mode 100644 arch/riscv/kernel/kernel_mode_vector.c

Comments

Charlie Jenkins Dec. 15, 2023, 6:24 a.m. UTC | #1

On Thu, Dec 14, 2023 at 03:57:16PM +0000, Andy Chiu wrote:
> From: Greentime Hu <[e-mail]>
> 
> Add kernel_vector_begin() and kernel_vector_end() function declarations
> and corresponding definitions in kernel_mode_vector.c
> 
> These are needed to wrap uses of vector in kernel mode.
> 
> Co-developed-by: Vincent Chen <[e-mail]>
> Signed-off-by: Vincent Chen <[e-mail]>
> Signed-off-by: Greentime Hu <[e-mail]>
> Signed-off-by: Andy Chiu <[e-mail]>
> ---
> Changelog v4:
>  - Use kernel_v_flags and helpers to track vector context.
> Changelog v3:
>  - Reorder patch 1 to patch 3 to make use of
>    {get,put}_cpu_vector_context later.
>  - Export {get,put}_cpu_vector_context.
>  - Save V context after disabling preemption. (Guo)
>  - Fix a build fail. (Conor)
>  - Remove irqs_disabled() check as it is not needed, fix styling. (Björn)
> Changelog v2:
>  - 's/kernel_rvv/kernel_vector' and return void in kernel_vector_begin
>    (Conor)
>  - export may_use_simd to include/asm/simd.h
> ---
>  arch/riscv/include/asm/processor.h     | 15 +++-
>  arch/riscv/include/asm/simd.h          | 42 ++++++++++++
>  arch/riscv/include/asm/vector.h        | 21 ++++++
>  arch/riscv/kernel/Makefile             |  1 +
>  arch/riscv/kernel/kernel_mode_vector.c | 95 ++++++++++++++++++++++++++
>  arch/riscv/kernel/process.c            |  2 +-
>  6 files changed, 174 insertions(+), 2 deletions(-)
>  create mode 100644 arch/riscv/include/asm/simd.h
>  create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
> 
> diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> index f19f861cda54..a47763c262e1 100644
> --- a/arch/riscv/include/asm/processor.h
> +++ b/arch/riscv/include/asm/processor.h
> @@ -73,6 +73,18 @@
>  struct task_struct;
>  struct pt_regs;
>  
> +/*
> + * We use a flag to track in-kernel Vector context. Currently the flag has the
> + * following meaning:
> + *
> + *  - bit 0 indicates whether the in-kernel Vector context is active. The
> + *    activation of this state disables the preemption.
> + */
> +
> +#define RISCV_KERNEL_MODE_V_MASK	0x1
> +
> +#define RISCV_KERNEL_MODE_V	0x1
> +
>  /* CPU-specific state of a task */
>  struct thread_struct {
>  	/* Callee-saved registers */
> @@ -81,7 +93,8 @@ struct thread_struct {
>  	unsigned long s[12];	/* s[0]: frame pointer */
>  	struct __riscv_d_ext_state fstate;
>  	unsigned long bad_cause;
> -	unsigned long vstate_ctrl;
> +	u32 riscv_v_flags;
> +	u32 vstate_ctrl;
>  	struct __riscv_v_ext_state vstate;
>  	unsigned long align_ctl;
>  };
> diff --git a/arch/riscv/include/asm/simd.h b/arch/riscv/include/asm/simd.h
> new file mode 100644
> index 000000000000..269752bfa2cc
> --- /dev/null
> +++ b/arch/riscv/include/asm/simd.h
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2017 Linaro Ltd. <[e-mail]>
> + * Copyright (C) 2023 SiFive
> + */
> +
> +#ifndef __ASM_SIMD_H
> +#define __ASM_SIMD_H
> +
> +#include <linux/compiler.h>
> +#include <linux/irqflags.h>
> +#include <linux/percpu.h>
> +#include <linux/preempt.h>
> +#include <linux/types.h>
> +
> +#ifdef CONFIG_RISCV_ISA_V
> +/*
> + * may_use_simd - whether it is allowable at this time to issue vector
> + *                instructions or access the vector register file
> + *
> + * Callers must not assume that the result remains true beyond the next
> + * preempt_enable() or return from softirq context.
> + */
> +static __must_check inline bool may_use_simd(void)
> +{
> +	/*
> +	 * RISCV_KERNEL_MODE_V is only set while preemption is disabled,
> +	 * and is clear whenever preemption is enabled.
> +	 */
> +	return !in_hardirq() && !in_nmi() && !(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);
> +}
> +
> +#else /* ! CONFIG_RISCV_ISA_V */
> +
> +static __must_check inline bool may_use_simd(void)
> +{
> +	return false;
> +}
> +
> +#endif /* ! CONFIG_RISCV_ISA_V */
> +
> +#endif
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index 87aaef656257..6254830c0668 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -22,6 +22,27 @@
>  extern unsigned long riscv_v_vsize;
>  int riscv_v_setup_vsize(void);
>  bool riscv_v_first_use_handler(struct pt_regs *regs);
> +void kernel_vector_begin(void);
> +void kernel_vector_end(void);
> +void get_cpu_vector_context(void);
> +void put_cpu_vector_context(void);
> +
> +static inline void riscv_v_ctx_cnt_add(u32 offset)
> +{
> +	current->thread.riscv_v_flags += offset;
> +	barrier();
> +}
> +
> +static inline void riscv_v_ctx_cnt_sub(u32 offset)
> +{
> +	barrier();
> +	current->thread.riscv_v_flags -= offset;
> +}
> +
> +static inline u32 riscv_v_ctx_cnt(void)
> +{
> +	return READ_ONCE(current->thread.riscv_v_flags);
> +}
>  
>  static __always_inline bool has_vector(void)
>  {
> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> index fee22a3d1b53..8c58595696b3 100644
> --- a/arch/riscv/kernel/Makefile
> +++ b/arch/riscv/kernel/Makefile
> @@ -63,6 +63,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/
>  obj-$(CONFIG_RISCV_MISALIGNED)	+= traps_misaligned.o
>  obj-$(CONFIG_FPU)		+= fpu.o
>  obj-$(CONFIG_RISCV_ISA_V)	+= vector.o
> +obj-$(CONFIG_RISCV_ISA_V)	+= kernel_mode_vector.o
>  obj-$(CONFIG_SMP)		+= smpboot.o
>  obj-$(CONFIG_SMP)		+= smp.o
>  obj-$(CONFIG_SMP)		+= cpu_ops.o
> diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c
> new file mode 100644
> index 000000000000..c9ccf21dd16c
> --- /dev/null
> +++ b/arch/riscv/kernel/kernel_mode_vector.c
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (C) 2012 ARM Ltd.
> + * Author: Catalin Marinas <[e-mail]>
> + * Copyright (C) 2017 Linaro Ltd. <[e-mail]>
> + * Copyright (C) 2021 SiFive
> + */
> +#include <linux/compiler.h>
> +#include <linux/irqflags.h>
> +#include <linux/percpu.h>
> +#include <linux/preempt.h>
> +#include <linux/types.h>
> +
> +#include <asm/vector.h>
> +#include <asm/switch_to.h>
> +#include <asm/simd.h>
> +
> +/*
> + * Claim ownership of the CPU vector context for use by the calling context.
> + *
> + * The caller may freely manipulate the vector context metadata until
> + * put_cpu_vector_context() is called.
> + */
> +void get_cpu_vector_context(void)
> +{
> +	preempt_disable();
> +
> +	WARN_ON(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);

This is a bigger issue than a warn. Calling riscv_v_ctx_cnt_add with
the same flag an even number of times will cause (riscv_v_ctx_cnt() &
RISCV_KERNEL_MODE_V_MASK) to return 0, even though vector is being used.
This could be solved by using a bitwise or instead of addition when
setting the flag.

> +	riscv_v_ctx_cnt_add(RISCV_KERNEL_MODE_V);
> +}
> +
> +/*
> + * Release the CPU vector context.
> + *
> + * Must be called from a context in which get_cpu_vector_context() was
> + * previously called, with no call to put_cpu_vector_context() in the
> + * meantime.
> + */
> +void put_cpu_vector_context(void)
> +{
> +	WARN_ON(!(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK));
> +	riscv_v_ctx_cnt_sub(RISCV_KERNEL_MODE_V);
> +
> +	preempt_enable();
> +}
> +
> +/*
> + * kernel_vector_begin(): obtain the CPU vector registers for use by the calling
> + * context
> + *
> + * Must not be called unless may_use_simd() returns true.
> + * Task context in the vector registers is saved back to memory as necessary.
> + *
> + * A matching call to kernel_vector_end() must be made before returning from the
> + * calling context.
> + *
> + * The caller may freely use the vector registers until kernel_vector_end() is
> + * called.
> + */
> +void kernel_vector_begin(void)
> +{
> +	if (WARN_ON(!has_vector()))

Should this be WARN_ONCE? If somebody runs a kernel compiled with vector
on hardware without vector, this warning has the potential to be thrown
an excessive amount of times.

> +		return;
> +
> +	BUG_ON(!may_use_simd());
> +
> +	get_cpu_vector_context();
> +
> +	riscv_v_vstate_save(current, task_pt_regs(current));
> +
> +	riscv_v_enable();
> +}
> +EXPORT_SYMBOL_GPL(kernel_vector_begin);
> +
> +/*
> + * kernel_vector_end(): give the CPU vector registers back to the current task
> + *
> + * Must be called from a context in which kernel_vector_begin() was previously
> + * called, with no call to kernel_vector_end() in the meantime.
> + *
> + * The caller must not use the vector registers after this function is called,
> + * unless kernel_vector_begin() is called again in the meantime.
> + */
> +void kernel_vector_end(void)
> +{
> +	if (WARN_ON(!has_vector()))

Same as above.

- Charlie

>+		return;
> +
> +	riscv_v_vstate_restore(current, task_pt_regs(current));
> +
> +	riscv_v_disable();
> +
> +	put_cpu_vector_context();
> +}
> +EXPORT_SYMBOL_GPL(kernel_vector_end);
> diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
> index 4f21d970a129..5c4dcf518684 100644
> --- a/arch/riscv/kernel/process.c
> +++ b/arch/riscv/kernel/process.c
> @@ -187,7 +187,6 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
>  	*dst = *src;
>  	/* clear entire V context, including datap for a new task */
>  	memset(&dst->thread.vstate, 0, sizeof(struct __riscv_v_ext_state));
> -
>  	return 0;
>  }
>  
> @@ -221,6 +220,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
>  		childregs->a0 = 0; /* Return value of fork() */
>  		p->thread.s[0] = 0;
>  	}
> +	p->thread.riscv_v_flags = 0;
>  	p->thread.ra = (unsigned long)ret_from_fork;
>  	p->thread.sp = (unsigned long)childregs; /* kernel sp */
>  	return 0;
> -- 
> 2.17.1
>

Andy Chiu Dec. 15, 2023, 4:01 p.m. UTC | #2

On Fri, Dec 15, 2023 at 2:24 PM Charlie Jenkins <[e-mail]> wrote:
>
> On Thu, Dec 14, 2023 at 03:57:16PM +0000, Andy Chiu wrote:
> > From: Greentime Hu <[e-mail]>
> >
> > Add kernel_vector_begin() and kernel_vector_end() function declarations
> > and corresponding definitions in kernel_mode_vector.c
> >
> > These are needed to wrap uses of vector in kernel mode.
> >
> > Co-developed-by: Vincent Chen <[e-mail]>
> > Signed-off-by: Vincent Chen <[e-mail]>
> > Signed-off-by: Greentime Hu <[e-mail]>
> > Signed-off-by: Andy Chiu <[e-mail]>
> > ---
> > Changelog v4:
> >  - Use kernel_v_flags and helpers to track vector context.
> > Changelog v3:
> >  - Reorder patch 1 to patch 3 to make use of
> >    {get,put}_cpu_vector_context later.
> >  - Export {get,put}_cpu_vector_context.
> >  - Save V context after disabling preemption. (Guo)
> >  - Fix a build fail. (Conor)
> >  - Remove irqs_disabled() check as it is not needed, fix styling. (Björn)
> > Changelog v2:
> >  - 's/kernel_rvv/kernel_vector' and return void in kernel_vector_begin
> >    (Conor)
> >  - export may_use_simd to include/asm/simd.h
> > ---
> >  arch/riscv/include/asm/processor.h     | 15 +++-
> >  arch/riscv/include/asm/simd.h          | 42 ++++++++++++
> >  arch/riscv/include/asm/vector.h        | 21 ++++++
> >  arch/riscv/kernel/Makefile             |  1 +
> >  arch/riscv/kernel/kernel_mode_vector.c | 95 ++++++++++++++++++++++++++
> >  arch/riscv/kernel/process.c            |  2 +-
> >  6 files changed, 174 insertions(+), 2 deletions(-)
> >  create mode 100644 arch/riscv/include/asm/simd.h
> >  create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
> >
> > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> > index f19f861cda54..a47763c262e1 100644
> > --- a/arch/riscv/include/asm/processor.h
> > +++ b/arch/riscv/include/asm/processor.h
> > @@ -73,6 +73,18 @@
> >  struct task_struct;
> >  struct pt_regs;
> >
> > +/*
> > + * We use a flag to track in-kernel Vector context. Currently the flag has the
> > + * following meaning:
> > + *
> > + *  - bit 0 indicates whether the in-kernel Vector context is active. The
> > + *    activation of this state disables the preemption.
> > + */
> > +
> > +#define RISCV_KERNEL_MODE_V_MASK     0x1
> > +
> > +#define RISCV_KERNEL_MODE_V  0x1
> > +
> >  /* CPU-specific state of a task */
> >  struct thread_struct {
> >       /* Callee-saved registers */
> > @@ -81,7 +93,8 @@ struct thread_struct {
> >       unsigned long s[12];    /* s[0]: frame pointer */
> >       struct __riscv_d_ext_state fstate;
> >       unsigned long bad_cause;
> > -     unsigned long vstate_ctrl;
> > +     u32 riscv_v_flags;
> > +     u32 vstate_ctrl;
> >       struct __riscv_v_ext_state vstate;
> >       unsigned long align_ctl;
> >  };
> > diff --git a/arch/riscv/include/asm/simd.h b/arch/riscv/include/asm/simd.h
> > new file mode 100644
> > index 000000000000..269752bfa2cc
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/simd.h
> > @@ -0,0 +1,42 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (C) 2017 Linaro Ltd. <[e-mail]>
> > + * Copyright (C) 2023 SiFive
> > + */
> > +
> > +#ifndef __ASM_SIMD_H
> > +#define __ASM_SIMD_H
> > +
> > +#include <linux/compiler.h>
> > +#include <linux/irqflags.h>
> > +#include <linux/percpu.h>
> > +#include <linux/preempt.h>
> > +#include <linux/types.h>
> > +
> > +#ifdef CONFIG_RISCV_ISA_V
> > +/*
> > + * may_use_simd - whether it is allowable at this time to issue vector
> > + *                instructions or access the vector register file
> > + *
> > + * Callers must not assume that the result remains true beyond the next
> > + * preempt_enable() or return from softirq context.
> > + */
> > +static __must_check inline bool may_use_simd(void)
> > +{
> > +     /*
> > +      * RISCV_KERNEL_MODE_V is only set while preemption is disabled,
> > +      * and is clear whenever preemption is enabled.
> > +      */
> > +     return !in_hardirq() && !in_nmi() && !(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);
> > +}
> > +
> > +#else /* ! CONFIG_RISCV_ISA_V */
> > +
> > +static __must_check inline bool may_use_simd(void)
> > +{
> > +     return false;
> > +}
> > +
> > +#endif /* ! CONFIG_RISCV_ISA_V */
> > +
> > +#endif
> > diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> > index 87aaef656257..6254830c0668 100644
> > --- a/arch/riscv/include/asm/vector.h
> > +++ b/arch/riscv/include/asm/vector.h
> > @@ -22,6 +22,27 @@
> >  extern unsigned long riscv_v_vsize;
> >  int riscv_v_setup_vsize(void);
> >  bool riscv_v_first_use_handler(struct pt_regs *regs);
> > +void kernel_vector_begin(void);
> > +void kernel_vector_end(void);
> > +void get_cpu_vector_context(void);
> > +void put_cpu_vector_context(void);
> > +
> > +static inline void riscv_v_ctx_cnt_add(u32 offset)
> > +{
> > +     current->thread.riscv_v_flags += offset;
> > +     barrier();
> > +}
> > +
> > +static inline void riscv_v_ctx_cnt_sub(u32 offset)
> > +{
> > +     barrier();
> > +     current->thread.riscv_v_flags -= offset;
> > +}
> > +
> > +static inline u32 riscv_v_ctx_cnt(void)
> > +{
> > +     return READ_ONCE(current->thread.riscv_v_flags);
> > +}
> >
> >  static __always_inline bool has_vector(void)
> >  {
> > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> > index fee22a3d1b53..8c58595696b3 100644
> > --- a/arch/riscv/kernel/Makefile
> > +++ b/arch/riscv/kernel/Makefile
> > @@ -63,6 +63,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/
> >  obj-$(CONFIG_RISCV_MISALIGNED)       += traps_misaligned.o
> >  obj-$(CONFIG_FPU)            += fpu.o
> >  obj-$(CONFIG_RISCV_ISA_V)    += vector.o
> > +obj-$(CONFIG_RISCV_ISA_V)    += kernel_mode_vector.o
> >  obj-$(CONFIG_SMP)            += smpboot.o
> >  obj-$(CONFIG_SMP)            += smp.o
> >  obj-$(CONFIG_SMP)            += cpu_ops.o
> > diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c
> > new file mode 100644
> > index 000000000000..c9ccf21dd16c
> > --- /dev/null
> > +++ b/arch/riscv/kernel/kernel_mode_vector.c
> > @@ -0,0 +1,95 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +/*
> > + * Copyright (C) 2012 ARM Ltd.
> > + * Author: Catalin Marinas <[e-mail]>
> > + * Copyright (C) 2017 Linaro Ltd. <[e-mail]>
> > + * Copyright (C) 2021 SiFive
> > + */
> > +#include <linux/compiler.h>
> > +#include <linux/irqflags.h>
> > +#include <linux/percpu.h>
> > +#include <linux/preempt.h>
> > +#include <linux/types.h>
> > +
> > +#include <asm/vector.h>
> > +#include <asm/switch_to.h>
> > +#include <asm/simd.h>
> > +
> > +/*
> > + * Claim ownership of the CPU vector context for use by the calling context.
> > + *
> > + * The caller may freely manipulate the vector context metadata until
> > + * put_cpu_vector_context() is called.
> > + */
> > +void get_cpu_vector_context(void)
> > +{
> > +     preempt_disable();
> > +
> > +     WARN_ON(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);
>
> This is a bigger issue than a warn. Calling riscv_v_ctx_cnt_add with
> the same flag an even number of times will cause (riscv_v_ctx_cnt() &
> RISCV_KERNEL_MODE_V_MASK) to return 0, even though vector is being used.
> This could be solved by using a bitwise or instead of addition when
> setting the flag.

Yes, we should use bitwise to operate it. At the same time, I am
thinking if we should allow calling kernel_vector_begin() multiple
times on a call chain. Or provide a fast check (in_kernel_vector()) in
a vectorized function to reduce the cost of calling multiple
kernel_vector_begin(). For example,

kernel_vector_begin()
memcpy()<- allow calling kernel_vector_begin/end() again
                  - or prevent calling it again with in_kernel_vector()
do_something_with_vector()
kernel_vector_end()

>
> > +     riscv_v_ctx_cnt_add(RISCV_KERNEL_MODE_V);
> > +}
> > +
> > +/*
> > + * Release the CPU vector context.
> > + *
> > + * Must be called from a context in which get_cpu_vector_context() was
> > + * previously called, with no call to put_cpu_vector_context() in the
> > + * meantime.
> > + */
> > +void put_cpu_vector_context(void)
> > +{
> > +     WARN_ON(!(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK));
> > +     riscv_v_ctx_cnt_sub(RISCV_KERNEL_MODE_V);
> > +
> > +     preempt_enable();
> > +}
> > +
> > +/*
> > + * kernel_vector_begin(): obtain the CPU vector registers for use by the calling
> > + * context
> > + *
> > + * Must not be called unless may_use_simd() returns true.
> > + * Task context in the vector registers is saved back to memory as necessary.
> > + *
> > + * A matching call to kernel_vector_end() must be made before returning from the
> > + * calling context.
> > + *
> > + * The caller may freely use the vector registers until kernel_vector_end() is
> > + * called.
> > + */
> > +void kernel_vector_begin(void)
> > +{
> > +     if (WARN_ON(!has_vector()))
>
> Should this be WARN_ONCE? If somebody runs a kernel compiled with vector
> on hardware without vector, this warning has the potential to be thrown
> an excessive amount of times.

Callers of this function should check with may_use_simd() and only
proceed to call this function if it returns true.

>
> > +             return;
> > +
> > +     BUG_ON(!may_use_simd());
> > +
> > +     get_cpu_vector_context();
> > +
> > +     riscv_v_vstate_save(current, task_pt_regs(current));
> > +
> > +     riscv_v_enable();
> > +}
> > +EXPORT_SYMBOL_GPL(kernel_vector_begin);
> > +
> > +/*
> > + * kernel_vector_end(): give the CPU vector registers back to the current task
> > + *
> > + * Must be called from a context in which kernel_vector_begin() was previously
> > + * called, with no call to kernel_vector_end() in the meantime.
> > + *
> > + * The caller must not use the vector registers after this function is called,
> > + * unless kernel_vector_begin() is called again in the meantime.
> > + */
> > +void kernel_vector_end(void)
> > +{
> > +     if (WARN_ON(!has_vector()))
>
> Same as above.
>
> - Charlie
>
> >+              return;
> > +
> > +     riscv_v_vstate_restore(current, task_pt_regs(current));
> > +
> > +     riscv_v_disable();
> > +
> > +     put_cpu_vector_context();
> > +}
> > +EXPORT_SYMBOL_GPL(kernel_vector_end);
> > diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
> > index 4f21d970a129..5c4dcf518684 100644
> > --- a/arch/riscv/kernel/process.c
> > +++ b/arch/riscv/kernel/process.c
> > @@ -187,7 +187,6 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
> >       *dst = *src;
> >       /* clear entire V context, including datap for a new task */
> >       memset(&dst->thread.vstate, 0, sizeof(struct __riscv_v_ext_state));
> > -
> >       return 0;
> >  }
> >
> > @@ -221,6 +220,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
> >               childregs->a0 = 0; /* Return value of fork() */
> >               p->thread.s[0] = 0;
> >       }
> > +     p->thread.riscv_v_flags = 0;
> >       p->thread.ra = (unsigned long)ret_from_fork;
> >       p->thread.sp = (unsigned long)childregs; /* kernel sp */
> >       return 0;
> > --
> > 2.17.1
> >

Regards,
Andy

Charlie Jenkins Dec. 15, 2023, 6:41 p.m. UTC | #3

On Sat, Dec 16, 2023 at 12:01:53AM +0800, Andy Chiu wrote:
> On Fri, Dec 15, 2023 at 2:24 PM Charlie Jenkins <[e-mail]> wrote:
> >
> > On Thu, Dec 14, 2023 at 03:57:16PM +0000, Andy Chiu wrote:
> > > From: Greentime Hu <[e-mail]>
> > >
> > > Add kernel_vector_begin() and kernel_vector_end() function declarations
> > > and corresponding definitions in kernel_mode_vector.c
> > >
> > > These are needed to wrap uses of vector in kernel mode.
> > >
> > > Co-developed-by: Vincent Chen <[e-mail]>
> > > Signed-off-by: Vincent Chen <[e-mail]>
> > > Signed-off-by: Greentime Hu <[e-mail]>
> > > Signed-off-by: Andy Chiu <[e-mail]>
> > > ---
> > > Changelog v4:
> > >  - Use kernel_v_flags and helpers to track vector context.
> > > Changelog v3:
> > >  - Reorder patch 1 to patch 3 to make use of
> > >    {get,put}_cpu_vector_context later.
> > >  - Export {get,put}_cpu_vector_context.
> > >  - Save V context after disabling preemption. (Guo)
> > >  - Fix a build fail. (Conor)
> > >  - Remove irqs_disabled() check as it is not needed, fix styling. (Björn)
> > > Changelog v2:
> > >  - 's/kernel_rvv/kernel_vector' and return void in kernel_vector_begin
> > >    (Conor)
> > >  - export may_use_simd to include/asm/simd.h
> > > ---
> > >  arch/riscv/include/asm/processor.h     | 15 +++-
> > >  arch/riscv/include/asm/simd.h          | 42 ++++++++++++
> > >  arch/riscv/include/asm/vector.h        | 21 ++++++
> > >  arch/riscv/kernel/Makefile             |  1 +
> > >  arch/riscv/kernel/kernel_mode_vector.c | 95 ++++++++++++++++++++++++++
> > >  arch/riscv/kernel/process.c            |  2 +-
> > >  6 files changed, 174 insertions(+), 2 deletions(-)
> > >  create mode 100644 arch/riscv/include/asm/simd.h
> > >  create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
> > >
> > > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> > > index f19f861cda54..a47763c262e1 100644
> > > --- a/arch/riscv/include/asm/processor.h
> > > +++ b/arch/riscv/include/asm/processor.h
> > > @@ -73,6 +73,18 @@
> > >  struct task_struct;
> > >  struct pt_regs;
> > >
> > > +/*
> > > + * We use a flag to track in-kernel Vector context. Currently the flag has the
> > > + * following meaning:
> > > + *
> > > + *  - bit 0 indicates whether the in-kernel Vector context is active. The
> > > + *    activation of this state disables the preemption.
> > > + */
> > > +
> > > +#define RISCV_KERNEL_MODE_V_MASK     0x1
> > > +
> > > +#define RISCV_KERNEL_MODE_V  0x1
> > > +
> > >  /* CPU-specific state of a task */
> > >  struct thread_struct {
> > >       /* Callee-saved registers */
> > > @@ -81,7 +93,8 @@ struct thread_struct {
> > >       unsigned long s[12];    /* s[0]: frame pointer */
> > >       struct __riscv_d_ext_state fstate;
> > >       unsigned long bad_cause;
> > > -     unsigned long vstate_ctrl;
> > > +     u32 riscv_v_flags;
> > > +     u32 vstate_ctrl;
> > >       struct __riscv_v_ext_state vstate;
> > >       unsigned long align_ctl;
> > >  };
> > > diff --git a/arch/riscv/include/asm/simd.h b/arch/riscv/include/asm/simd.h
> > > new file mode 100644
> > > index 000000000000..269752bfa2cc
> > > --- /dev/null
> > > +++ b/arch/riscv/include/asm/simd.h
> > > @@ -0,0 +1,42 @@
> > > +/* SPDX-License-Identifier: GPL-2.0-only */
> > > +/*
> > > + * Copyright (C) 2017 Linaro Ltd. <[e-mail]>
> > > + * Copyright (C) 2023 SiFive
> > > + */
> > > +
> > > +#ifndef __ASM_SIMD_H
> > > +#define __ASM_SIMD_H
> > > +
> > > +#include <linux/compiler.h>
> > > +#include <linux/irqflags.h>
> > > +#include <linux/percpu.h>
> > > +#include <linux/preempt.h>
> > > +#include <linux/types.h>
> > > +
> > > +#ifdef CONFIG_RISCV_ISA_V
> > > +/*
> > > + * may_use_simd - whether it is allowable at this time to issue vector
> > > + *                instructions or access the vector register file
> > > + *
> > > + * Callers must not assume that the result remains true beyond the next
> > > + * preempt_enable() or return from softirq context.
> > > + */
> > > +static __must_check inline bool may_use_simd(void)
> > > +{
> > > +     /*
> > > +      * RISCV_KERNEL_MODE_V is only set while preemption is disabled,
> > > +      * and is clear whenever preemption is enabled.
> > > +      */
> > > +     return !in_hardirq() && !in_nmi() && !(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);
> > > +}
> > > +
> > > +#else /* ! CONFIG_RISCV_ISA_V */
> > > +
> > > +static __must_check inline bool may_use_simd(void)
> > > +{
> > > +     return false;
> > > +}
> > > +
> > > +#endif /* ! CONFIG_RISCV_ISA_V */
> > > +
> > > +#endif
> > > diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> > > index 87aaef656257..6254830c0668 100644
> > > --- a/arch/riscv/include/asm/vector.h
> > > +++ b/arch/riscv/include/asm/vector.h
> > > @@ -22,6 +22,27 @@
> > >  extern unsigned long riscv_v_vsize;
> > >  int riscv_v_setup_vsize(void);
> > >  bool riscv_v_first_use_handler(struct pt_regs *regs);
> > > +void kernel_vector_begin(void);
> > > +void kernel_vector_end(void);
> > > +void get_cpu_vector_context(void);
> > > +void put_cpu_vector_context(void);
> > > +
> > > +static inline void riscv_v_ctx_cnt_add(u32 offset)
> > > +{
> > > +     current->thread.riscv_v_flags += offset;
> > > +     barrier();
> > > +}
> > > +
> > > +static inline void riscv_v_ctx_cnt_sub(u32 offset)
> > > +{
> > > +     barrier();
> > > +     current->thread.riscv_v_flags -= offset;
> > > +}
> > > +
> > > +static inline u32 riscv_v_ctx_cnt(void)
> > > +{
> > > +     return READ_ONCE(current->thread.riscv_v_flags);
> > > +}
> > >
> > >  static __always_inline bool has_vector(void)
> > >  {
> > > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> > > index fee22a3d1b53..8c58595696b3 100644
> > > --- a/arch/riscv/kernel/Makefile
> > > +++ b/arch/riscv/kernel/Makefile
> > > @@ -63,6 +63,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/
> > >  obj-$(CONFIG_RISCV_MISALIGNED)       += traps_misaligned.o
> > >  obj-$(CONFIG_FPU)            += fpu.o
> > >  obj-$(CONFIG_RISCV_ISA_V)    += vector.o
> > > +obj-$(CONFIG_RISCV_ISA_V)    += kernel_mode_vector.o
> > >  obj-$(CONFIG_SMP)            += smpboot.o
> > >  obj-$(CONFIG_SMP)            += smp.o
> > >  obj-$(CONFIG_SMP)            += cpu_ops.o
> > > diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c
> > > new file mode 100644
> > > index 000000000000..c9ccf21dd16c
> > > --- /dev/null
> > > +++ b/arch/riscv/kernel/kernel_mode_vector.c
> > > @@ -0,0 +1,95 @@
> > > +// SPDX-License-Identifier: GPL-2.0-or-later
> > > +/*
> > > + * Copyright (C) 2012 ARM Ltd.
> > > + * Author: Catalin Marinas <[e-mail]>
> > > + * Copyright (C) 2017 Linaro Ltd. <[e-mail]>
> > > + * Copyright (C) 2021 SiFive
> > > + */
> > > +#include <linux/compiler.h>
> > > +#include <linux/irqflags.h>
> > > +#include <linux/percpu.h>
> > > +#include <linux/preempt.h>
> > > +#include <linux/types.h>
> > > +
> > > +#include <asm/vector.h>
> > > +#include <asm/switch_to.h>
> > > +#include <asm/simd.h>
> > > +
> > > +/*
> > > + * Claim ownership of the CPU vector context for use by the calling context.
> > > + *
> > > + * The caller may freely manipulate the vector context metadata until
> > > + * put_cpu_vector_context() is called.
> > > + */
> > > +void get_cpu_vector_context(void)
> > > +{
> > > +     preempt_disable();
> > > +
> > > +     WARN_ON(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);
> >
> > This is a bigger issue than a warn. Calling riscv_v_ctx_cnt_add with
> > the same flag an even number of times will cause (riscv_v_ctx_cnt() &
> > RISCV_KERNEL_MODE_V_MASK) to return 0, even though vector is being used.
> > This could be solved by using a bitwise or instead of addition when
> > setting the flag.
> 
> Yes, we should use bitwise to operate it. At the same time, I am
> thinking if we should allow calling kernel_vector_begin() multiple
> times on a call chain. Or provide a fast check (in_kernel_vector()) in
> a vectorized function to reduce the cost of calling multiple
> kernel_vector_begin(). For example,
> 
> kernel_vector_begin()
> memcpy()<- allow calling kernel_vector_begin/end() again
>                   - or prevent calling it again with in_kernel_vector()
> do_something_with_vector()
> kernel_vector_end()
> 

Yes that seems like that could be useful.

> >
> > > +     riscv_v_ctx_cnt_add(RISCV_KERNEL_MODE_V);
> > > +}
> > > +
> > > +/*
> > > + * Release the CPU vector context.
> > > + *
> > > + * Must be called from a context in which get_cpu_vector_context() was
> > > + * previously called, with no call to put_cpu_vector_context() in the
> > > + * meantime.
> > > + */
> > > +void put_cpu_vector_context(void)
> > > +{
> > > +     WARN_ON(!(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK));
> > > +     riscv_v_ctx_cnt_sub(RISCV_KERNEL_MODE_V);
> > > +
> > > +     preempt_enable();
> > > +}
> > > +
> > > +/*
> > > + * kernel_vector_begin(): obtain the CPU vector registers for use by the calling
> > > + * context
> > > + *
> > > + * Must not be called unless may_use_simd() returns true.
> > > + * Task context in the vector registers is saved back to memory as necessary.
> > > + *
> > > + * A matching call to kernel_vector_end() must be made before returning from the
> > > + * calling context.
> > > + *
> > > + * The caller may freely use the vector registers until kernel_vector_end() is
> > > + * called.
> > > + */
> > > +void kernel_vector_begin(void)
> > > +{
> > > +     if (WARN_ON(!has_vector()))
> >
> > Should this be WARN_ONCE? If somebody runs a kernel compiled with vector
> > on hardware without vector, this warning has the potential to be thrown
> > an excessive amount of times.
> 
> Callers of this function should check with may_use_simd() and only
> proceed to call this function if it returns true.
> 

Yes it is a bug if they don't call may_use_simd() first, but I was more
concerned about the number of logs that are generated with WARN_ON.
A single log seems like it would be sufficient.

- Charlie

> >
> > > +             return;
> > > +
> > > +     BUG_ON(!may_use_simd());
> > > +
> > > +     get_cpu_vector_context();
> > > +
> > > +     riscv_v_vstate_save(current, task_pt_regs(current));
> > > +
> > > +     riscv_v_enable();
> > > +}
> > > +EXPORT_SYMBOL_GPL(kernel_vector_begin);
> > > +
> > > +/*
> > > + * kernel_vector_end(): give the CPU vector registers back to the current task
> > > + *
> > > + * Must be called from a context in which kernel_vector_begin() was previously
> > > + * called, with no call to kernel_vector_end() in the meantime.
> > > + *
> > > + * The caller must not use the vector registers after this function is called,
> > > + * unless kernel_vector_begin() is called again in the meantime.
> > > + */
> > > +void kernel_vector_end(void)
> > > +{
> > > +     if (WARN_ON(!has_vector()))
> >
> > Same as above.
> >
> > - Charlie
> >
> > >+              return;
> > > +
> > > +     riscv_v_vstate_restore(current, task_pt_regs(current));
> > > +
> > > +     riscv_v_disable();
> > > +
> > > +     put_cpu_vector_context();
> > > +}
> > > +EXPORT_SYMBOL_GPL(kernel_vector_end);
> > > diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
> > > index 4f21d970a129..5c4dcf518684 100644
> > > --- a/arch/riscv/kernel/process.c
> > > +++ b/arch/riscv/kernel/process.c
> > > @@ -187,7 +187,6 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
> > >       *dst = *src;
> > >       /* clear entire V context, including datap for a new task */
> > >       memset(&dst->thread.vstate, 0, sizeof(struct __riscv_v_ext_state));
> > > -
> > >       return 0;
> > >  }
> > >
> > > @@ -221,6 +220,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
> > >               childregs->a0 = 0; /* Return value of fork() */
> > >               p->thread.s[0] = 0;
> > >       }
> > > +     p->thread.riscv_v_flags = 0;
> > >       p->thread.ra = (unsigned long)ret_from_fork;
> > >       p->thread.sp = (unsigned long)childregs; /* kernel sp */
> > >       return 0;
> > > --
> > > 2.17.1
> > >
> 
> Regards,
> Andy

Andy Chiu Dec. 19, 2023, 6:04 a.m. UTC | #4

On Sat, Dec 16, 2023 at 2:41 AM Charlie Jenkins <[e-mail]> wrote:
>
> On Sat, Dec 16, 2023 at 12:01:53AM +0800, Andy Chiu wrote:
> > On Fri, Dec 15, 2023 at 2:24 PM Charlie Jenkins <[e-mail]> wrote:
> > >
> > > On Thu, Dec 14, 2023 at 03:57:16PM +0000, Andy Chiu wrote:
> > > > From: Greentime Hu <[e-mail]>
> > > >
> > > > Add kernel_vector_begin() and kernel_vector_end() function declarations
> > > > and corresponding definitions in kernel_mode_vector.c
> > > >
> > > > These are needed to wrap uses of vector in kernel mode.
> > > >
> > > > Co-developed-by: Vincent Chen <[e-mail]>
> > > > Signed-off-by: Vincent Chen <[e-mail]>
> > > > Signed-off-by: Greentime Hu <[e-mail]>
> > > > Signed-off-by: Andy Chiu <[e-mail]>
> > > > ---
> > > > Changelog v4:
> > > >  - Use kernel_v_flags and helpers to track vector context.
> > > > Changelog v3:
> > > >  - Reorder patch 1 to patch 3 to make use of
> > > >    {get,put}_cpu_vector_context later.
> > > >  - Export {get,put}_cpu_vector_context.
> > > >  - Save V context after disabling preemption. (Guo)
> > > >  - Fix a build fail. (Conor)
> > > >  - Remove irqs_disabled() check as it is not needed, fix styling. (Björn)
> > > > Changelog v2:
> > > >  - 's/kernel_rvv/kernel_vector' and return void in kernel_vector_begin
> > > >    (Conor)
> > > >  - export may_use_simd to include/asm/simd.h
> > > > ---
> > > >  arch/riscv/include/asm/processor.h     | 15 +++-
> > > >  arch/riscv/include/asm/simd.h          | 42 ++++++++++++
> > > >  arch/riscv/include/asm/vector.h        | 21 ++++++
> > > >  arch/riscv/kernel/Makefile             |  1 +
> > > >  arch/riscv/kernel/kernel_mode_vector.c | 95 ++++++++++++++++++++++++++
> > > >  arch/riscv/kernel/process.c            |  2 +-
> > > >  6 files changed, 174 insertions(+), 2 deletions(-)
> > > >  create mode 100644 arch/riscv/include/asm/simd.h
> > > >  create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
> > > >
> > > > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> > > > index f19f861cda54..a47763c262e1 100644
> > > > --- a/arch/riscv/include/asm/processor.h
> > > > +++ b/arch/riscv/include/asm/processor.h
> > > > @@ -73,6 +73,18 @@
> > > >  struct task_struct;
> > > >  struct pt_regs;
> > > >
> > > > +/*
> > > > + * We use a flag to track in-kernel Vector context. Currently the flag has the
> > > > + * following meaning:
> > > > + *
> > > > + *  - bit 0 indicates whether the in-kernel Vector context is active. The
> > > > + *    activation of this state disables the preemption.
> > > > + */
> > > > +
> > > > +#define RISCV_KERNEL_MODE_V_MASK     0x1
> > > > +
> > > > +#define RISCV_KERNEL_MODE_V  0x1
> > > > +
> > > >  /* CPU-specific state of a task */
> > > >  struct thread_struct {
> > > >       /* Callee-saved registers */
> > > > @@ -81,7 +93,8 @@ struct thread_struct {
> > > >       unsigned long s[12];    /* s[0]: frame pointer */
> > > >       struct __riscv_d_ext_state fstate;
> > > >       unsigned long bad_cause;
> > > > -     unsigned long vstate_ctrl;
> > > > +     u32 riscv_v_flags;
> > > > +     u32 vstate_ctrl;
> > > >       struct __riscv_v_ext_state vstate;
> > > >       unsigned long align_ctl;
> > > >  };
> > > > diff --git a/arch/riscv/include/asm/simd.h b/arch/riscv/include/asm/simd.h
> > > > new file mode 100644
> > > > index 000000000000..269752bfa2cc
> > > > --- /dev/null
> > > > +++ b/arch/riscv/include/asm/simd.h
> > > > @@ -0,0 +1,42 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0-only */
> > > > +/*
> > > > + * Copyright (C) 2017 Linaro Ltd. <[e-mail]>
> > > > + * Copyright (C) 2023 SiFive
> > > > + */
> > > > +
> > > > +#ifndef __ASM_SIMD_H
> > > > +#define __ASM_SIMD_H
> > > > +
> > > > +#include <linux/compiler.h>
> > > > +#include <linux/irqflags.h>
> > > > +#include <linux/percpu.h>
> > > > +#include <linux/preempt.h>
> > > > +#include <linux/types.h>
> > > > +
> > > > +#ifdef CONFIG_RISCV_ISA_V
> > > > +/*
> > > > + * may_use_simd - whether it is allowable at this time to issue vector
> > > > + *                instructions or access the vector register file
> > > > + *
> > > > + * Callers must not assume that the result remains true beyond the next
> > > > + * preempt_enable() or return from softirq context.
> > > > + */
> > > > +static __must_check inline bool may_use_simd(void)
> > > > +{
> > > > +     /*
> > > > +      * RISCV_KERNEL_MODE_V is only set while preemption is disabled,
> > > > +      * and is clear whenever preemption is enabled.
> > > > +      */
> > > > +     return !in_hardirq() && !in_nmi() && !(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);
> > > > +}
> > > > +
> > > > +#else /* ! CONFIG_RISCV_ISA_V */
> > > > +
> > > > +static __must_check inline bool may_use_simd(void)
> > > > +{
> > > > +     return false;
> > > > +}
> > > > +
> > > > +#endif /* ! CONFIG_RISCV_ISA_V */
> > > > +
> > > > +#endif
> > > > diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> > > > index 87aaef656257..6254830c0668 100644
> > > > --- a/arch/riscv/include/asm/vector.h
> > > > +++ b/arch/riscv/include/asm/vector.h
> > > > @@ -22,6 +22,27 @@
> > > >  extern unsigned long riscv_v_vsize;
> > > >  int riscv_v_setup_vsize(void);
> > > >  bool riscv_v_first_use_handler(struct pt_regs *regs);
> > > > +void kernel_vector_begin(void);
> > > > +void kernel_vector_end(void);
> > > > +void get_cpu_vector_context(void);
> > > > +void put_cpu_vector_context(void);
> > > > +
> > > > +static inline void riscv_v_ctx_cnt_add(u32 offset)
> > > > +{
> > > > +     current->thread.riscv_v_flags += offset;
> > > > +     barrier();
> > > > +}
> > > > +
> > > > +static inline void riscv_v_ctx_cnt_sub(u32 offset)
> > > > +{
> > > > +     barrier();
> > > > +     current->thread.riscv_v_flags -= offset;
> > > > +}
> > > > +
> > > > +static inline u32 riscv_v_ctx_cnt(void)
> > > > +{
> > > > +     return READ_ONCE(current->thread.riscv_v_flags);
> > > > +}
> > > >
> > > >  static __always_inline bool has_vector(void)
> > > >  {
> > > > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> > > > index fee22a3d1b53..8c58595696b3 100644
> > > > --- a/arch/riscv/kernel/Makefile
> > > > +++ b/arch/riscv/kernel/Makefile
> > > > @@ -63,6 +63,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/
> > > >  obj-$(CONFIG_RISCV_MISALIGNED)       += traps_misaligned.o
> > > >  obj-$(CONFIG_FPU)            += fpu.o
> > > >  obj-$(CONFIG_RISCV_ISA_V)    += vector.o
> > > > +obj-$(CONFIG_RISCV_ISA_V)    += kernel_mode_vector.o
> > > >  obj-$(CONFIG_SMP)            += smpboot.o
> > > >  obj-$(CONFIG_SMP)            += smp.o
> > > >  obj-$(CONFIG_SMP)            += cpu_ops.o
> > > > diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c
> > > > new file mode 100644
> > > > index 000000000000..c9ccf21dd16c
> > > > --- /dev/null
> > > > +++ b/arch/riscv/kernel/kernel_mode_vector.c
> > > > @@ -0,0 +1,95 @@
> > > > +// SPDX-License-Identifier: GPL-2.0-or-later
> > > > +/*
> > > > + * Copyright (C) 2012 ARM Ltd.
> > > > + * Author: Catalin Marinas <[e-mail]>
> > > > + * Copyright (C) 2017 Linaro Ltd. <[e-mail]>
> > > > + * Copyright (C) 2021 SiFive
> > > > + */
> > > > +#include <linux/compiler.h>
> > > > +#include <linux/irqflags.h>
> > > > +#include <linux/percpu.h>
> > > > +#include <linux/preempt.h>
> > > > +#include <linux/types.h>
> > > > +
> > > > +#include <asm/vector.h>
> > > > +#include <asm/switch_to.h>
> > > > +#include <asm/simd.h>
> > > > +
> > > > +/*
> > > > + * Claim ownership of the CPU vector context for use by the calling context.
> > > > + *
> > > > + * The caller may freely manipulate the vector context metadata until
> > > > + * put_cpu_vector_context() is called.
> > > > + */
> > > > +void get_cpu_vector_context(void)
> > > > +{
> > > > +     preempt_disable();
> > > > +
> > > > +     WARN_ON(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);
> > >
> > > This is a bigger issue than a warn. Calling riscv_v_ctx_cnt_add with
> > > the same flag an even number of times will cause (riscv_v_ctx_cnt() &
> > > RISCV_KERNEL_MODE_V_MASK) to return 0, even though vector is being used.
> > > This could be solved by using a bitwise or instead of addition when
> > > setting the flag.
> >
> > Yes, we should use bitwise to operate it. At the same time, I am
> > thinking if we should allow calling kernel_vector_begin() multiple
> > times on a call chain. Or provide a fast check (in_kernel_vector()) in
> > a vectorized function to reduce the cost of calling multiple
> > kernel_vector_begin(). For example,
> >
> > kernel_vector_begin()
> > memcpy()<- allow calling kernel_vector_begin/end() again
> >                   - or prevent calling it again with in_kernel_vector()
> > do_something_with_vector()
> > kernel_vector_end()
> >
>
> Yes that seems like that could be useful.
>
> > >
> > > > +     riscv_v_ctx_cnt_add(RISCV_KERNEL_MODE_V);
> > > > +}
> > > > +
> > > > +/*
> > > > + * Release the CPU vector context.
> > > > + *
> > > > + * Must be called from a context in which get_cpu_vector_context() was
> > > > + * previously called, with no call to put_cpu_vector_context() in the
> > > > + * meantime.
> > > > + */
> > > > +void put_cpu_vector_context(void)
> > > > +{
> > > > +     WARN_ON(!(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK));
> > > > +     riscv_v_ctx_cnt_sub(RISCV_KERNEL_MODE_V);
> > > > +
> > > > +     preempt_enable();
> > > > +}
> > > > +
> > > > +/*
> > > > + * kernel_vector_begin(): obtain the CPU vector registers for use by the calling
> > > > + * context
> > > > + *
> > > > + * Must not be called unless may_use_simd() returns true.
> > > > + * Task context in the vector registers is saved back to memory as necessary.
> > > > + *
> > > > + * A matching call to kernel_vector_end() must be made before returning from the
> > > > + * calling context.
> > > > + *
> > > > + * The caller may freely use the vector registers until kernel_vector_end() is
> > > > + * called.
> > > > + */
> > > > +void kernel_vector_begin(void)
> > > > +{
> > > > +     if (WARN_ON(!has_vector()))
> > >
> > > Should this be WARN_ONCE? If somebody runs a kernel compiled with vector
> > > on hardware without vector, this warning has the potential to be thrown
> > > an excessive amount of times.
> >
> > Callers of this function should check with may_use_simd() and only
> > proceed to call this function if it returns true.
> >
>
> Yes it is a bug if they don't call may_use_simd() first, but I was more
> concerned about the number of logs that are generated with WARN_ON.
> A single log seems like it would be sufficient.

In fact this will just panic the kernel if a user proceeds
kernel_vector_begin() regardless of may_use_simd(). To demonstrate,
has_vector() returns false under these conditions:
1. The kernel is compiled without CONFIG_RISCV_ISA_V.
2. The kernel has CONFIG_RISCV_ISA_V but the hardware doesn't support V
3. The kernel has CONFIG_RISCV_ISA_V. The hardware supports V, but in
a way where it is not recognized by the kernel, e.g uneven VLEN.
For case 1, kernel_vector_begin() won't even exist so the user will
experience a compile failure.
For case 2 and 3, the kernel will panic, hitting an illegal
instruction error when it starts executing V because VS will be off by
then. Unless the user goes very off and manually enables V by calling
riscv_v_enable() on case 3.

Please tell me if you still have any concerns about this.

>
> - Charlie
>
> > >
> > > > +             return;
> > > > +
> > > > +     BUG_ON(!may_use_simd());
> > > > +
> > > > +     get_cpu_vector_context();
> > > > +
> > > > +     riscv_v_vstate_save(current, task_pt_regs(current));
> > > > +
> > > > +     riscv_v_enable();
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(kernel_vector_begin);
> > > > +
> > > > +/*
> > > > + * kernel_vector_end(): give the CPU vector registers back to the current task
> > > > + *
> > > > + * Must be called from a context in which kernel_vector_begin() was previously
> > > > + * called, with no call to kernel_vector_end() in the meantime.
> > > > + *
> > > > + * The caller must not use the vector registers after this function is called,
> > > > + * unless kernel_vector_begin() is called again in the meantime.
> > > > + */
> > > > +void kernel_vector_end(void)
> > > > +{
> > > > +     if (WARN_ON(!has_vector()))
> > >
> > > Same as above.
> > >
> > > - Charlie
> > >
> > > >+              return;
> > > > +
> > > > +     riscv_v_vstate_restore(current, task_pt_regs(current));
> > > > +
> > > > +     riscv_v_disable();
> > > > +
> > > > +     put_cpu_vector_context();
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(kernel_vector_end);
> > > > diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
> > > > index 4f21d970a129..5c4dcf518684 100644
> > > > --- a/arch/riscv/kernel/process.c
> > > > +++ b/arch/riscv/kernel/process.c
> > > > @@ -187,7 +187,6 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
> > > >       *dst = *src;
> > > >       /* clear entire V context, including datap for a new task */
> > > >       memset(&dst->thread.vstate, 0, sizeof(struct __riscv_v_ext_state));
> > > > -
> > > >       return 0;
> > > >  }
> > > >
> > > > @@ -221,6 +220,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
> > > >               childregs->a0 = 0; /* Return value of fork() */
> > > >               p->thread.s[0] = 0;
> > > >       }
> > > > +     p->thread.riscv_v_flags = 0;
> > > >       p->thread.ra = (unsigned long)ret_from_fork;
> > > >       p->thread.sp = (unsigned long)childregs; /* kernel sp */
> > > >       return 0;
> > > > --
> > > > 2.17.1
> > > >
> >
> > Regards,
> > Andy

Patch

diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index f19f861cda54..a47763c262e1 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -73,6 +73,18 @@ 
 struct task_struct;
 struct pt_regs;
 
+/*
+ * We use a flag to track in-kernel Vector context. Currently the flag has the
+ * following meaning:
+ *
+ *  - bit 0 indicates whether the in-kernel Vector context is active. The
+ *    activation of this state disables the preemption.
+ */
+
+#define RISCV_KERNEL_MODE_V_MASK	0x1
+
+#define RISCV_KERNEL_MODE_V	0x1
+
 /* CPU-specific state of a task */
 struct thread_struct {
 	/* Callee-saved registers */
@@ -81,7 +93,8 @@  struct thread_struct {
 	unsigned long s[12];	/* s[0]: frame pointer */
 	struct __riscv_d_ext_state fstate;
 	unsigned long bad_cause;
-	unsigned long vstate_ctrl;
+	u32 riscv_v_flags;
+	u32 vstate_ctrl;
 	struct __riscv_v_ext_state vstate;
 	unsigned long align_ctl;
 };
diff --git a/arch/riscv/include/asm/simd.h b/arch/riscv/include/asm/simd.h
new file mode 100644
index 000000000000..269752bfa2cc
--- /dev/null
+++ b/arch/riscv/include/asm/simd.h
@@ -0,0 +1,42 @@ 
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2017 Linaro Ltd. <[e-mail]>
+ * Copyright (C) 2023 SiFive
+ */
+
+#ifndef __ASM_SIMD_H
+#define __ASM_SIMD_H
+
+#include <linux/compiler.h>
+#include <linux/irqflags.h>
+#include <linux/percpu.h>
+#include <linux/preempt.h>
+#include <linux/types.h>
+
+#ifdef CONFIG_RISCV_ISA_V
+/*
+ * may_use_simd - whether it is allowable at this time to issue vector
+ *                instructions or access the vector register file
+ *
+ * Callers must not assume that the result remains true beyond the next
+ * preempt_enable() or return from softirq context.
+ */
+static __must_check inline bool may_use_simd(void)
+{
+	/*
+	 * RISCV_KERNEL_MODE_V is only set while preemption is disabled,
+	 * and is clear whenever preemption is enabled.
+	 */
+	return !in_hardirq() && !in_nmi() && !(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);
+}
+
+#else /* ! CONFIG_RISCV_ISA_V */
+
+static __must_check inline bool may_use_simd(void)
+{
+	return false;
+}
+
+#endif /* ! CONFIG_RISCV_ISA_V */
+
+#endif
diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index 87aaef656257..6254830c0668 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -22,6 +22,27 @@ 
 extern unsigned long riscv_v_vsize;
 int riscv_v_setup_vsize(void);
 bool riscv_v_first_use_handler(struct pt_regs *regs);
+void kernel_vector_begin(void);
+void kernel_vector_end(void);
+void get_cpu_vector_context(void);
+void put_cpu_vector_context(void);
+
+static inline void riscv_v_ctx_cnt_add(u32 offset)
+{
+	current->thread.riscv_v_flags += offset;
+	barrier();
+}
+
+static inline void riscv_v_ctx_cnt_sub(u32 offset)
+{
+	barrier();
+	current->thread.riscv_v_flags -= offset;
+}
+
+static inline u32 riscv_v_ctx_cnt(void)
+{
+	return READ_ONCE(current->thread.riscv_v_flags);
+}
 
 static __always_inline bool has_vector(void)
 {
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index fee22a3d1b53..8c58595696b3 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -63,6 +63,7 @@  obj-$(CONFIG_MMU) += vdso.o vdso/
 obj-$(CONFIG_RISCV_MISALIGNED)	+= traps_misaligned.o
 obj-$(CONFIG_FPU)		+= fpu.o
 obj-$(CONFIG_RISCV_ISA_V)	+= vector.o
+obj-$(CONFIG_RISCV_ISA_V)	+= kernel_mode_vector.o
 obj-$(CONFIG_SMP)		+= smpboot.o
 obj-$(CONFIG_SMP)		+= smp.o
 obj-$(CONFIG_SMP)		+= cpu_ops.o
diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c
new file mode 100644
index 000000000000..c9ccf21dd16c
--- /dev/null
+++ b/arch/riscv/kernel/kernel_mode_vector.c
@@ -0,0 +1,95 @@ 
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Catalin Marinas <[e-mail]>
+ * Copyright (C) 2017 Linaro Ltd. <[e-mail]>
+ * Copyright (C) 2021 SiFive
+ */
+#include <linux/compiler.h>
+#include <linux/irqflags.h>
+#include <linux/percpu.h>
+#include <linux/preempt.h>
+#include <linux/types.h>
+
+#include <asm/vector.h>
+#include <asm/switch_to.h>
+#include <asm/simd.h>
+
+/*
+ * Claim ownership of the CPU vector context for use by the calling context.
+ *
+ * The caller may freely manipulate the vector context metadata until
+ * put_cpu_vector_context() is called.
+ */
+void get_cpu_vector_context(void)
+{
+	preempt_disable();
+
+	WARN_ON(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK);
+	riscv_v_ctx_cnt_add(RISCV_KERNEL_MODE_V);
+}
+
+/*
+ * Release the CPU vector context.
+ *
+ * Must be called from a context in which get_cpu_vector_context() was
+ * previously called, with no call to put_cpu_vector_context() in the
+ * meantime.
+ */
+void put_cpu_vector_context(void)
+{
+	WARN_ON(!(riscv_v_ctx_cnt() & RISCV_KERNEL_MODE_V_MASK));
+	riscv_v_ctx_cnt_sub(RISCV_KERNEL_MODE_V);
+
+	preempt_enable();
+}
+
+/*
+ * kernel_vector_begin(): obtain the CPU vector registers for use by the calling
+ * context
+ *
+ * Must not be called unless may_use_simd() returns true.
+ * Task context in the vector registers is saved back to memory as necessary.
+ *
+ * A matching call to kernel_vector_end() must be made before returning from the
+ * calling context.
+ *
+ * The caller may freely use the vector registers until kernel_vector_end() is
+ * called.
+ */
+void kernel_vector_begin(void)
+{
+	if (WARN_ON(!has_vector()))
+		return;
+
+	BUG_ON(!may_use_simd());
+
+	get_cpu_vector_context();
+
+	riscv_v_vstate_save(current, task_pt_regs(current));
+
+	riscv_v_enable();
+}
+EXPORT_SYMBOL_GPL(kernel_vector_begin);
+
+/*
+ * kernel_vector_end(): give the CPU vector registers back to the current task
+ *
+ * Must be called from a context in which kernel_vector_begin() was previously
+ * called, with no call to kernel_vector_end() in the meantime.
+ *
+ * The caller must not use the vector registers after this function is called,
+ * unless kernel_vector_begin() is called again in the meantime.
+ */
+void kernel_vector_end(void)
+{
+	if (WARN_ON(!has_vector()))
+		return;
+
+	riscv_v_vstate_restore(current, task_pt_regs(current));
+
+	riscv_v_disable();
+
+	put_cpu_vector_context();
+}
+EXPORT_SYMBOL_GPL(kernel_vector_end);
diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
index 4f21d970a129..5c4dcf518684 100644
--- a/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
@@ -187,7 +187,6 @@  int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
 	*dst = *src;
 	/* clear entire V context, including datap for a new task */
 	memset(&dst->thread.vstate, 0, sizeof(struct __riscv_v_ext_state));
-
 	return 0;
 }
 
@@ -221,6 +220,7 @@  int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
 		childregs->a0 = 0; /* Return value of fork() */
 		p->thread.s[0] = 0;
 	}
+	p->thread.riscv_v_flags = 0;
 	p->thread.ra = (unsigned long)ret_from_fork;
 	p->thread.sp = (unsigned long)childregs; /* kernel sp */
 	return 0;