| Message ID | 20231130151932.729708-1-emil.renner.berthing@canonical.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add JH7100 errata and update device tree | expand |
From: Conor Dooley <conor.dooley@microchip.com> On Thu, 30 Nov 2023 16:19:24 +0100, Emil Renner Berthing wrote: > Now that the driver for the SiFive cache controller supports manual > flushing as non-standard cache operations[1] we can add an errata option > for the StarFive JH7100 SoC and update the device tree with the cache > controller, dedicated DMA pool and add MMC nodes for the SD-card and > wifi. > > This series needs the following commit in [1] to work properly: > > [...] Applied to riscv-cache-for-next, thanks! [1/8] riscv: errata: Add StarFive JH7100 errata https://git.kernel.org/conor/c/64fc984a8a54 Thanks, Conor.
Hi Conor, On Wed, Dec 13, 2023 at 4:43 PM Conor Dooley <conor@kernel.org> wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > On Thu, 30 Nov 2023 16:19:24 +0100, Emil Renner Berthing wrote: > > Now that the driver for the SiFive cache controller supports manual > > flushing as non-standard cache operations[1] we can add an errata option > > for the StarFive JH7100 SoC and update the device tree with the cache > > controller, dedicated DMA pool and add MMC nodes for the SD-card and > > wifi. > > > > This series needs the following commit in [1] to work properly: > > > > [...] > > Applied to riscv-cache-for-next, thanks! > > [1/8] riscv: errata: Add StarFive JH7100 errata > https://git.kernel.org/conor/c/64fc984a8a54 That's the one which also needs depends on !DMA_DIRECT_REMAP? Gr{oetje,eeting}s, Geert
From: Conor Dooley <conor.dooley@microchip.com> On Thu, 30 Nov 2023 16:19:24 +0100, Emil Renner Berthing wrote: > Now that the driver for the SiFive cache controller supports manual > flushing as non-standard cache operations[1] we can add an errata option > for the StarFive JH7100 SoC and update the device tree with the cache > controller, dedicated DMA pool and add MMC nodes for the SD-card and > wifi. > > This series needs the following commit in [1] to work properly: > > [...] Applied to riscv-dt-for-next, thanks! [2/8] riscv: dts: starfive: Group tuples in interrupt properties https://git.kernel.org/conor/c/dd3c1b365fe9 [3/8] riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs https://git.kernel.org/conor/c/ba0074972ee9 [4/8] riscv: dts: starfive: Add JH7100 cache controller https://git.kernel.org/conor/c/d4b95c445cab [5/8] riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards https://git.kernel.org/conor/c/0a99b562e815 [6/8] riscv: dts: starfive: Add JH7100 MMC nodes https://git.kernel.org/conor/c/a29bb6564e12 [7/8] riscv: dts: starfive: Enable SD-card on JH7100 boards https://git.kernel.org/conor/c/c548409cfe03 [8/8] riscv: dts: starfive: Enable SDIO wifi on JH7100 boards https://git.kernel.org/conor/c/56b10953da7e Thanks, Conor.
Geert Uytterhoeven wrote: > Hi Conor, > > On Wed, Dec 13, 2023 at 4:43 PM Conor Dooley <conor@kernel.org> wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > > > On Thu, 30 Nov 2023 16:19:24 +0100, Emil Renner Berthing wrote: > > > Now that the driver for the SiFive cache controller supports manual > > > flushing as non-standard cache operations[1] we can add an errata option > > > for the StarFive JH7100 SoC and update the device tree with the cache > > > controller, dedicated DMA pool and add MMC nodes for the SD-card and > > > wifi. > > > > > > This series needs the following commit in [1] to work properly: > > > > > > [...] > > > > Applied to riscv-cache-for-next, thanks! > > > > [1/8] riscv: errata: Add StarFive JH7100 errata > > https://git.kernel.org/conor/c/64fc984a8a54 > > That's the one which also needs depends on !DMA_DIRECT_REMAP? Yes, thanks. I sent a fix now: https://lore.kernel.org/linux-riscv/20231215190909.3722757-1-emil.renner.berthing@canonical.com/ /Emil
Now that the driver for the SiFive cache controller supports manual flushing as non-standard cache operations[1] we can add an errata option for the StarFive JH7100 SoC and update the device tree with the cache controller, dedicated DMA pool and add MMC nodes for the SD-card and wifi. This series needs the following commit in [1] to work properly: 0d5701dc9cd6 ("soc: sifive: ccache: Add StarFive JH7100 support") ..and its parent for dtb_checks to pass. [1]: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=riscv-soc-for-next Changes in v2: - Add Conor's ack on patch 1/8 - Add my SoB on patch 2/8 - Update commit message on patch 4/8 Emil Renner Berthing (7): riscv: errata: Add StarFive JH7100 errata riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs riscv: dts: starfive: Add JH7100 cache controller riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards riscv: dts: starfive: Add JH7100 MMC nodes riscv: dts: starfive: Enable SD-card on JH7100 boards riscv: dts: starfive: Enable SDIO wifi on JH7100 boards Geert Uytterhoeven (1): riscv: dts: starfive: Group tuples in interrupt properties arch/riscv/Kconfig.errata | 17 +++ .../boot/dts/starfive/jh7100-common.dtsi | 131 ++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 48 ++++++- 3 files changed, 192 insertions(+), 4 deletions(-)