| Message ID | 20231105200642.62792-1-marek.vasut+renesas@mailbox.org (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | clk: rs9: Fix DIF OEn bit placement on 9FGV0241 | expand |
Hi Maker, thanks for the patch. Am Sonntag, 5. November 2023, 21:06:15 CET schrieb Marek Vasut: > On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE1 is BIT(2), on the other > chips like 9FGV0441 and 9FGV0841 DIF OE0 is BIT(0) and so on. Increment > the index in BIT() macro instead of the result of BIT() macro to shift > the bit correctly on 9FGV0241. > > Fixes: 603df193ec51 ("clk: rs9: Support device specific dif bit > calculation") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> > --- > Cc: Alexander Stein <alexander.stein@ew.tq-group.com> > Cc: Conor Dooley <conor+dt@kernel.org> > Cc: Geert Uytterhoeven <geert+renesas@glider.be> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: devicetree@vger.kernel.org > Cc: linux-clk@vger.kernel.org > Cc: linux-renesas-soc@vger.kernel.org > --- > drivers/clk/clk-renesas-pcie.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c > index 380245f635d6..6606aba253c5 100644 > --- a/drivers/clk/clk-renesas-pcie.c > +++ b/drivers/clk/clk-renesas-pcie.c > @@ -163,7 +163,7 @@ static u8 rs9_calc_dif(const struct rs9_driver_data > *rs9, int idx) enum rs9_model model = rs9->chip_info->model; > > if (model == RENESAS_9FGV0241) > - return BIT(idx) + 1; > + return BIT(idx + 1); > else if (model == RENESAS_9FGV0441) > return BIT(idx); Nice catch! Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Quoting Marek Vasut (2023-11-05 12:06:15) > On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE1 is BIT(2), on the other > chips like 9FGV0441 and 9FGV0841 DIF OE0 is BIT(0) and so on. Increment > the index in BIT() macro instead of the result of BIT() macro to shift > the bit correctly on 9FGV0241. > > Fixes: 603df193ec51 ("clk: rs9: Support device specific dif bit calculation") > Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> > --- Applied to clk-next
diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c index 380245f635d6..6606aba253c5 100644 --- a/drivers/clk/clk-renesas-pcie.c +++ b/drivers/clk/clk-renesas-pcie.c @@ -163,7 +163,7 @@ static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx) enum rs9_model model = rs9->chip_info->model; if (model == RENESAS_9FGV0241) - return BIT(idx) + 1; + return BIT(idx + 1); else if (model == RENESAS_9FGV0441) return BIT(idx);
On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE1 is BIT(2), on the other chips like 9FGV0441 and 9FGV0841 DIF OE0 is BIT(0) and so on. Increment the index in BIT() macro instead of the result of BIT() macro to shift the bit correctly on 9FGV0241. Fixes: 603df193ec51 ("clk: rs9: Support device specific dif bit calculation") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> --- Cc: Alexander Stein <alexander.stein@ew.tq-group.com> Cc: Conor Dooley <conor+dt@kernel.org> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- drivers/clk/clk-renesas-pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)