| Message ID | 20231221102956.754617-1-c-vankar@ti.com |
|---|---|
| State | RFC |
| Headers | show |
| Series | [RFC,1/2] phy: ti: gmii-sel: Enable SGMII mode for J784S4 | expand |
On 21/12/2023 12:29, Chintan Vankar wrote: > TI's J784S4 SoC supports SGMII mode with the CPSW9G instance of the CPSW > Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the > corresponding extra_modes member. > > Signed-off-by: Chintan Vankar <c-vankar@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org>
On Thu, 21 Dec 2023 15:59:55 +0530, Chintan Vankar wrote: > TI's J784S4 SoC supports SGMII mode with the CPSW9G instance of the CPSW > Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the > corresponding extra_modes member. > > Applied, thanks! [1/2] phy: ti: gmii-sel: Enable SGMII mode for J784S4 commit: d719915ad9706a16adde231789a1d46fc12fb9c7 [2/2] phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J784S4 commit: 2029e71482fcd94dcc7df2c66c7fa635479748bf Best regards,
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index bc847d3879f7..0f4818adb440 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -248,7 +248,7 @@ static const struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { .use_of_data = true, .regfields = phy_gmii_sel_fields_am654, - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | BIT(PHY_INTERFACE_MODE_USXGMII), .num_ports = 8, .num_qsgmii_main_ports = 2,
TI's J784S4 SoC supports SGMII mode with the CPSW9G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by: Chintan Vankar <c-vankar@ti.com> --- drivers/phy/ti/phy-gmii-sel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)