| Message ID | 20231220211743.2490518-1-cristian.ciocaltea@collabora.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Enable networking support for StarFive JH7100 SoC | expand |
Cristian Ciocaltea wrote: > This patch series adds ethernet support for the StarFive JH7100 SoC and > makes it available for the StarFive VisionFive V1 and BeagleV Starlight > boards, although I could only validate on the former SBC. Thank you Emil > and Geert for helping with tests on BeagleV! > > The work is heavily based on the reference implementation [1] and depends > on the SiFive Composable Cache controller and non-coherent DMA support > provided by Emil via [2] and [3]. > > *Update 1*: As of next-20231214, dependencies [2] & [3] have been merged. > > *Update 2*: Since v5, the dwmac patches will be handled via [4], while the > clock patches subset via [5]. I'm not sure my rb my sense when I'm listed as a co-developer, but this version looks good to me: Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > [1] https://github.com/starfive-tech/linux/commits/visionfive > [2] https://lore.kernel.org/all/CAJM55Z_pdoGxRXbmBgJ5GbVWyeM1N6+LHihbNdT26Oo_qA5VYA@mail.gmail.com/ > [3] https://lore.kernel.org/all/20231130151932.729708-1-emil.renner.berthing@canonical.com/ > [4] https://lore.kernel.org/lkml/20231220002824.2462655-1-cristian.ciocaltea@collabora.com/ > [5] https://lore.kernel.org/lkml/20231219232442.2460166-1-cristian.ciocaltea@collabora.com/ > > Changes in v6: > - Applied alphabetical ordering in PATCH 3 and 4 (Emil) > > Changes in v5: > - Collected R-b tags from Jacob and Andrew > - Squashed PATCH 2 into PATCH 1 per Krzysztof's review > - Drop unsupported snps,no-pbl-x8 property from gmac DT node > - Split series into patch sets per subsystem, as described in "Update 2" > section above (per Andrew's review) > - v4: > https://lore.kernel.org/lkml/20231218214451.2345691-1-cristian.ciocaltea@collabora.com/ > > Changes in v4: > - Restricted double usage of 'ahb' reset name in PATCH 2 (Jessica, Samuel) > - Moved phy reference from PATCH 5 to both PATCH 6 & 7 where the node is > actually defined (Emil, Conor) > - Drop unnecessary gpio include in PATCH 6; also added a DTS comment > describing the rational behind RX internal delay adjustment (Andrew) > - v3: > https://lore.kernel.org/lkml/20231215204050.2296404-1-cristian.ciocaltea@collabora.com/ > > Changes in v3: > - Rebased series onto next-20231214 and dropped the ccache & DMA coherency > related patches (v2 06-08/12) handled by Emil via [3] > - Squashed PATCH v2 01/12 into PATCH v3 2/9, per Krzysztof's review > - Dropped incorrect PATCH v2 02/12 > - Incorporated Emil's feedback; also added his Co-developed-by on all dts > patches > - Documented the need of adjusting RX internal delay in PATCH v3 8/9, per > Andrew's request > - Added clock fixes from Emil (PATCH v3 8-9/9) required to support > 10/100Mb link speeds > - v2: > https://lore.kernel.org/lkml/20231029042712.520010-1-cristian.ciocaltea@collabora.com/ > > Changes in v2: > - Dropped ccache PATCH 01-05 reworked by Emil via [2] > - Dropped already applied PATCH 06/12 > - Added PATCH v2 01 to prepare snps-dwmac binding for JH7100 support > - Added PATCH v2 02-03 to provide some jh7110-dwmac binding optimizations > - Handled JH7110 conflicting work in PATCH 07 via PATCH v2 04 > - Reworked PATCH 8 via PATCH v2 05, adding JH7100 quirk and dropped > starfive,gtxclk-dlychain DT property; also fixed register naming > - Added PATCH v2 08 providing DMA coherency related DT changes > - Updated PATCH 9 commit msg: > s/OF_DMA_DEFAULT_COHERENT/ARCH_DMA_DEFAULT_COHERENT/ > - Replaced 'uncached-offset' property with 'sifive,cache-ops' in PATCH > 10/12 and dropped 'sideband' reg > - Add new patch providing coherent DMA memory pool (PATCH v2 10) > - Updated PATCH 11/12 according to the stmmac glue layer changes in > upstream > - Split PATCH 12/12 into PATCH v2 10-12 to handle individual gmac setup of > VisionFive v1 and BeagleV boards as they use different PHYs; also > switched phy-mode from "rgmii-tx" to "rgmii-id" (requires a reduction of > rx-internal-delay-ps by ~50%) > - Rebased series onto next-20231024 > - v1: > https://lore.kernel.org/lkml/20230211031821.976408-1-cristian.ciocaltea@collabora.com/ > > Cristian Ciocaltea (4): > riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes > riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac > riscv: dts: starfive: visionfive-v1: Setup ethernet phy > riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio > > .../dts/starfive/jh7100-beaglev-starlight.dts | 11 +++ > .../boot/dts/starfive/jh7100-common.dtsi | 84 +++++++++++++++++++ > .../jh7100-starfive-visionfive-v1.dts | 22 ++++- > arch/riscv/boot/dts/starfive/jh7100.dtsi | 36 ++++++++ > 4 files changed, 152 insertions(+), 1 deletion(-) > > -- > 2.43.0 >
On Tue, Dec 26, 2023 at 02:38:26PM -0600, Emil Renner Berthing wrote: > Cristian Ciocaltea wrote: > > This patch series adds ethernet support for the StarFive JH7100 SoC and > > makes it available for the StarFive VisionFive V1 and BeagleV Starlight > > boards, although I could only validate on the former SBC. Thank you Emil > > and Geert for helping with tests on BeagleV! > > > > The work is heavily based on the reference implementation [1] and depends > > on the SiFive Composable Cache controller and non-coherent DMA support > > provided by Emil via [2] and [3]. > > > > *Update 1*: As of next-20231214, dependencies [2] & [3] have been merged. > > > > *Update 2*: Since v5, the dwmac patches will be handled via [4], while the > > clock patches subset via [5]. > > I'm not sure my rb my sense when I'm listed as a co-developer, but this version > looks good to me: > > Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Cool, thanks. Cristian, can you ping this series once the binding gets picked up by the netdev folks after the merge window closes? Cheers, Conor.
On 1/10/24 15:57, Conor Dooley wrote: > On Tue, Dec 26, 2023 at 02:38:26PM -0600, Emil Renner Berthing wrote: >> Cristian Ciocaltea wrote: >>> This patch series adds ethernet support for the StarFive JH7100 SoC and >>> makes it available for the StarFive VisionFive V1 and BeagleV Starlight >>> boards, although I could only validate on the former SBC. Thank you Emil >>> and Geert for helping with tests on BeagleV! >>> >>> The work is heavily based on the reference implementation [1] and depends >>> on the SiFive Composable Cache controller and non-coherent DMA support >>> provided by Emil via [2] and [3]. >>> >>> *Update 1*: As of next-20231214, dependencies [2] & [3] have been merged. >>> >>> *Update 2*: Since v5, the dwmac patches will be handled via [4], while the >>> clock patches subset via [5]. >> >> I'm not sure my rb my sense when I'm listed as a co-developer, but this version >> looks good to me: >> >> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > Cool, thanks. Cristian, can you ping this series once the binding gets > picked up by the netdev folks after the merge window closes? Sure, will do! Thanks, Cristian > Cheers, > Conor.
Hi Conor, On 1/10/24 18:17, Cristian Ciocaltea wrote: > On 1/10/24 15:57, Conor Dooley wrote: >> On Tue, Dec 26, 2023 at 02:38:26PM -0600, Emil Renner Berthing wrote: >>> Cristian Ciocaltea wrote: >>>> This patch series adds ethernet support for the StarFive JH7100 SoC and >>>> makes it available for the StarFive VisionFive V1 and BeagleV Starlight >>>> boards, although I could only validate on the former SBC. Thank you Emil >>>> and Geert for helping with tests on BeagleV! >>>> >>>> The work is heavily based on the reference implementation [1] and depends >>>> on the SiFive Composable Cache controller and non-coherent DMA support >>>> provided by Emil via [2] and [3]. >>>> >>>> *Update 1*: As of next-20231214, dependencies [2] & [3] have been merged. >>>> >>>> *Update 2*: Since v5, the dwmac patches will be handled via [4], while the >>>> clock patches subset via [5]. >>> >>> I'm not sure my rb my sense when I'm listed as a co-developer, but this version >>> looks good to me: >>> >>> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> >> >> Cool, thanks. Cristian, can you ping this series once the binding gets >> picked up by the netdev folks after the merge window closes? > > Sure, will do! The binding has been applied on net-next [1]. Thanks, Cristian [1]: https://lore.kernel.org/lkml/170669882745.1676.8675995195978883744.git-patchwork-notify@kernel.org/
From: Conor Dooley <conor.dooley@microchip.com> On Wed, 20 Dec 2023 23:17:38 +0200, Cristian Ciocaltea wrote: > This patch series adds ethernet support for the StarFive JH7100 SoC and > makes it available for the StarFive VisionFive V1 and BeagleV Starlight > boards, although I could only validate on the former SBC. Thank you Emil > and Geert for helping with tests on BeagleV! > > The work is heavily based on the reference implementation [1] and depends > on the SiFive Composable Cache controller and non-coherent DMA support > provided by Emil via [2] and [3]. > > [...] Applied to riscv-dt-for-next, thanks! [1/4] riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes https://git.kernel.org/conor/c/5ca37ca2a483 [2/4] riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac https://git.kernel.org/conor/c/6e204aa2116c [3/4] riscv: dts: starfive: visionfive-v1: Setup ethernet phy https://git.kernel.org/conor/c/e16d3dc0a2d7 [4/4] riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio https://git.kernel.org/conor/c/2db68ddbf33a Thanks, Conor.
This patch series adds ethernet support for the StarFive JH7100 SoC and makes it available for the StarFive VisionFive V1 and BeagleV Starlight boards, although I could only validate on the former SBC. Thank you Emil and Geert for helping with tests on BeagleV! The work is heavily based on the reference implementation [1] and depends on the SiFive Composable Cache controller and non-coherent DMA support provided by Emil via [2] and [3]. *Update 1*: As of next-20231214, dependencies [2] & [3] have been merged. *Update 2*: Since v5, the dwmac patches will be handled via [4], while the clock patches subset via [5]. [1] https://github.com/starfive-tech/linux/commits/visionfive [2] https://lore.kernel.org/all/CAJM55Z_pdoGxRXbmBgJ5GbVWyeM1N6+LHihbNdT26Oo_qA5VYA@mail.gmail.com/ [3] https://lore.kernel.org/all/20231130151932.729708-1-emil.renner.berthing@canonical.com/ [4] https://lore.kernel.org/lkml/20231220002824.2462655-1-cristian.ciocaltea@collabora.com/ [5] https://lore.kernel.org/lkml/20231219232442.2460166-1-cristian.ciocaltea@collabora.com/ Changes in v6: - Applied alphabetical ordering in PATCH 3 and 4 (Emil) Changes in v5: - Collected R-b tags from Jacob and Andrew - Squashed PATCH 2 into PATCH 1 per Krzysztof's review - Drop unsupported snps,no-pbl-x8 property from gmac DT node - Split series into patch sets per subsystem, as described in "Update 2" section above (per Andrew's review) - v4: https://lore.kernel.org/lkml/20231218214451.2345691-1-cristian.ciocaltea@collabora.com/ Changes in v4: - Restricted double usage of 'ahb' reset name in PATCH 2 (Jessica, Samuel) - Moved phy reference from PATCH 5 to both PATCH 6 & 7 where the node is actually defined (Emil, Conor) - Drop unnecessary gpio include in PATCH 6; also added a DTS comment describing the rational behind RX internal delay adjustment (Andrew) - v3: https://lore.kernel.org/lkml/20231215204050.2296404-1-cristian.ciocaltea@collabora.com/ Changes in v3: - Rebased series onto next-20231214 and dropped the ccache & DMA coherency related patches (v2 06-08/12) handled by Emil via [3] - Squashed PATCH v2 01/12 into PATCH v3 2/9, per Krzysztof's review - Dropped incorrect PATCH v2 02/12 - Incorporated Emil's feedback; also added his Co-developed-by on all dts patches - Documented the need of adjusting RX internal delay in PATCH v3 8/9, per Andrew's request - Added clock fixes from Emil (PATCH v3 8-9/9) required to support 10/100Mb link speeds - v2: https://lore.kernel.org/lkml/20231029042712.520010-1-cristian.ciocaltea@collabora.com/ Changes in v2: - Dropped ccache PATCH 01-05 reworked by Emil via [2] - Dropped already applied PATCH 06/12 - Added PATCH v2 01 to prepare snps-dwmac binding for JH7100 support - Added PATCH v2 02-03 to provide some jh7110-dwmac binding optimizations - Handled JH7110 conflicting work in PATCH 07 via PATCH v2 04 - Reworked PATCH 8 via PATCH v2 05, adding JH7100 quirk and dropped starfive,gtxclk-dlychain DT property; also fixed register naming - Added PATCH v2 08 providing DMA coherency related DT changes - Updated PATCH 9 commit msg: s/OF_DMA_DEFAULT_COHERENT/ARCH_DMA_DEFAULT_COHERENT/ - Replaced 'uncached-offset' property with 'sifive,cache-ops' in PATCH 10/12 and dropped 'sideband' reg - Add new patch providing coherent DMA memory pool (PATCH v2 10) - Updated PATCH 11/12 according to the stmmac glue layer changes in upstream - Split PATCH 12/12 into PATCH v2 10-12 to handle individual gmac setup of VisionFive v1 and BeagleV boards as they use different PHYs; also switched phy-mode from "rgmii-tx" to "rgmii-id" (requires a reduction of rx-internal-delay-ps by ~50%) - Rebased series onto next-20231024 - v1: https://lore.kernel.org/lkml/20230211031821.976408-1-cristian.ciocaltea@collabora.com/ Cristian Ciocaltea (4): riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac riscv: dts: starfive: visionfive-v1: Setup ethernet phy riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio .../dts/starfive/jh7100-beaglev-starlight.dts | 11 +++ .../boot/dts/starfive/jh7100-common.dtsi | 84 +++++++++++++++++++ .../jh7100-starfive-visionfive-v1.dts | 22 ++++- arch/riscv/boot/dts/starfive/jh7100.dtsi | 36 ++++++++ 4 files changed, 152 insertions(+), 1 deletion(-)