| Message ID | 20231225044207.3821-2-jszhang@kernel.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | b6da6cbe13ebf24716438de71d50573b9f36f35d |
| Headers | show |
| Series | riscv: enable EFFICIENT_UNALIGNED_ACCESS and DCACHE_WORD_ACCESS | expand |
On Mon, Dec 25, 2023 at 12:42:06PM +0800, Jisheng Zhang wrote: > Some riscv implementations such as T-HEAD's C906, C908, C910 and C920 > support efficient unaligned access, for performance reason we want > to enable HAVE_EFFICIENT_UNALIGNED_ACCESS on these platforms. To > avoid performance regressions on other non efficient unaligned access > platforms, HAVE_EFFICIENT_UNALIGNED_ACCESS can't be globally selected. > > To solve this problem, runtime code patching based on the detected > speed is a good solution. But that's not easy, it involves lots of > work to modify vairous subsystems such as net, mm, lib and so on. > This can be done step by step. > > So let's take an easier solution: add support to efficient unaligned > access and hide the support under NONPORTABLE. > > Now let's introduce RISCV_EFFICIENT_UNALIGNED_ACCESS which depends on > NONPORTABLE, if users know during config time that the kernel will be > only run on those efficient unaligned access hw platforms, they can > enable it. Obviously, generic unified kernel Image shouldn't enable it. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> > --- > arch/riscv/Kconfig | 13 +++++++++++++ > arch/riscv/Makefile | 2 ++ > 2 files changed, 15 insertions(+) Reviewed-by: Eric Biggers <ebiggers@google.com> - Eric
From: Jisheng Zhang > Sent: 25 December 2023 04:42 > > Some riscv implementations such as T-HEAD's C906, C908, C910 and C920 > support efficient unaligned access, for performance reason we want > to enable HAVE_EFFICIENT_UNALIGNED_ACCESS on these platforms. To > avoid performance regressions on other non efficient unaligned access > platforms, HAVE_EFFICIENT_UNALIGNED_ACCESS can't be globally selected. How efficient are these EFFICIENT_UNALIGNED_ACCESS ? For single word accesses it doesn't matter much (since they don't fault). But for memcpy() (and similar) if they are slightly slow (eg the same as two aligned accesses) it is likely still worth doing misaligned transfers for both ends and aligned transfers for the middle. For example, on modern x86 it really isn't worth worrying about misaligned transfers of 64bit registers. AFAICT accesses within a cacheline just use byte enables - so are zero cost. Accesses that cross cache line boundaries do get split - but the out-of-order execute, store-buffer and the ability to do two reads in each clock cycle make the overall cost only just measurable. Not sure how the various RISC-V cpu compare though. You might get an extra clock delay a lot more often. So, while mostly you 'don't care' about the alignment, there may still be a few places where it does matter. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 24c1799e2ec4..afcc5fdc16f7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -651,6 +651,19 @@ config RISCV_MISALIGNED load/store for both kernel and userspace. When disable, misaligned accesses will generate SIGBUS in userspace and panic in kernel. +config RISCV_EFFICIENT_UNALIGNED_ACCESS + bool "Assume the CPU supports fast unaligned memory accesses" + depends on NONPORTABLE + select HAVE_EFFICIENT_UNALIGNED_ACCESS + help + Say Y here if you want the kernel to assume that the CPU supports + efficient unaligned memory accesses. When enabled, this option + improves the performance of the kernel on such CPUs. However, the + kernel will run much more slowly, or will not be able to run at all, + on CPUs that do not support efficient unaligned memory accesses. + + If unsure what to do here, say N. + endmenu # "Platform type" menu "Kernel features" diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index a74be78678eb..ebbe02628a27 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -108,7 +108,9 @@ KBUILD_AFLAGS_MODULE += $(call as-option,-Wa$(comma)-mno-relax) # unaligned accesses. While unaligned accesses are explicitly allowed in the # RISC-V ISA, they're emulated by machine mode traps on all extant # architectures. It's faster to have GCC emit only aligned accesses. +ifneq ($(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS),y) KBUILD_CFLAGS += $(call cc-option,-mstrict-align) +endif ifeq ($(CONFIG_STACKPROTECTOR_PER_TASK),y) prepare: stack_protector_prepare