diff mbox series

[RFC,28/30] riscv: dts: renesas: r9a07g043f: Add L2 cache node

Message ID 20231220230646.219816-29-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State New
Headers show
Series Add support for Renesas RZ/Five RISC-V SoC | expand

Commit Message

Lad Prabhakar Dec. 20, 2023, 11:06 p.m. UTC 
commit a38b1061d327c120844e5dc0217191b06ce3b25f upstream.

Add L2 cache node for RZ/Five SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929000704.53217-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Pavel Machek Dec. 26, 2023, 6:37 p.m. UTC | #1 
Hi!

> commit a38b1061d327c120844e5dc0217191b06ce3b25f upstream.
> 
> Add L2 cache node for RZ/Five SoC.

This is minor, but..

> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -29,6 +29,7 @@ cpu0: cpu@0 {
>  			i-cache-line-size = <0x40>;
>  			d-cache-size = <0x8000>;
>  			d-cache-line-size = <0x40>;
> @@ -56,4 +57,15 @@ plic: interrupt-controller@12c00000 {
>  		resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
>  		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
>  	};
> +
> +	l2cache: cache-controller@13400000 {
...
> +		cache-size = <0x40000>;
> +		cache-line-size = <64>;

Sometimes using hex and sometimes dec for cache-line-size looks
strange.

Best regards,
								Pavel
Lad Prabhakar Dec. 27, 2023, 4:08 p.m. UTC | #2 
Hi Pavel,

Thank you for the review.

> Hi!
> 
> > commit a38b1061d327c120844e5dc0217191b06ce3b25f upstream.
> >
> > Add L2 cache node for RZ/Five SoC.
> 
> This is minor, but..
> 
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > @@ -29,6 +29,7 @@ cpu0: cpu@0 {
> >  			i-cache-line-size = <0x40>;
> >  			d-cache-size = <0x8000>;
> >  			d-cache-line-size = <0x40>;
> > @@ -56,4 +57,15 @@ plic: interrupt-controller@12c00000 {
> >  		resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> >  		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> >  	};
> > +
> > +	l2cache: cache-controller@13400000 {
> ...
> > +		cache-size = <0x40000>;
> > +		cache-line-size = <64>;
> 
> Sometimes using hex and sometimes dec for cache-line-size looks strange.
> 
Agreed, If there arises a chance to change this file upstream I'll update it.

Cheers,
Prabhakar
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index 6ec1c6f9a403..c8d63a8f7d86 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -29,6 +29,7 @@  cpu0: cpu@0 {
 			i-cache-line-size = <0x40>;
 			d-cache-size = <0x8000>;
 			d-cache-line-size = <0x40>;
+			next-level-cache = <&l2cache>;
 			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
 			operating-points-v2 = <&cluster0_opp>;
 
@@ -56,4 +57,15 @@  plic: interrupt-controller@12c00000 {
 		resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
 		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
 	};
+
+	l2cache: cache-controller@13400000 {
+		compatible = "andestech,ax45mp-cache", "cache";
+		reg = <0x0 0x13400000 0x0 0x100000>;
+		interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
+		cache-size = <0x40000>;
+		cache-line-size = <64>;
+		cache-sets = <1024>;
+		cache-unified;
+		cache-level = <2>;
+	};
 };