| Message ID | 20231214072839.2367-20-minda.chen@starfivetech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Refactoring Microchip PCIe driver and add StarFive PCIe | expand |
On Thu, Dec 14, 2023 at 03:28:37PM +0800, Minda Chen wrote: > From: Kevin Xie <kevin.xie@starfivetech.com> > > Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum > waiting time between exit from a conventional reset and sending the > first configuration request to the device. > > As described in PCI base specification r6.0, section 6.6.1 <Conventional > Reset>, there are two different use cases of the value: > > - "With a Downstream Port that does not support Link speeds greater > than 5.0 GT/s, software must wait a minimum of 100 ms following exit > from a Conventional Reset before sending a Configuration Request to > the device immediately below that Port." > > - "With a Downstream Port that supports Link speeds greater than > 5.0 GT/s, software must wait a minimum of 100 ms after Link training > completes before sending a Configuration Request to the device > immediately below that Port." > > Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com> > Reviewed-by: Mason Huo <mason.huo@starfivetech.com> > --- > drivers/pci/pci.h | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) This needs Bjorn's ack. Thanks, Lorenzo > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > index 5ecbcf041179..06f1f1eb878c 100644 > --- a/drivers/pci/pci.h > +++ b/drivers/pci/pci.h > @@ -22,6 +22,22 @@ > */ > #define PCIE_PME_TO_L2_TIMEOUT_US 10000 > > +/* > + * As described in PCI base specification r6.0, section 6.6.1 <Conventional > + * Reset>, there are two different use cases of the value: > + * > + * - "With a Downstream Port that does not support Link speeds greater > + * than 5.0 GT/s, software must wait a minimum of 100 ms following exit > + * from a Conventional Reset before sending a Configuration Request to > + * the device immediately below that Port." > + * > + * - "With a Downstream Port that supports Link speeds greater than > + * 5.0 GT/s, software must wait a minimum of 100 ms after Link training > + * completes before sending a Configuration Request to the device > + * immediately below that Port." > + */ > +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 > + > extern const unsigned char pcie_link_speed[]; > extern bool pci_early_dump; > > -- > 2.17.1 >
On Thu, Dec 14, 2023 at 03:28:37PM +0800, Minda Chen wrote: > From: Kevin Xie <kevin.xie@starfivetech.com> > > Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum > waiting time between exit from a conventional reset and sending the > first configuration request to the device. > > As described in PCI base specification r6.0, section 6.6.1 <Conventional > Reset>, there are two different use cases of the value: > > - "With a Downstream Port that does not support Link speeds greater > than 5.0 GT/s, software must wait a minimum of 100 ms following exit > from a Conventional Reset before sending a Configuration Request to > the device immediately below that Port." > > - "With a Downstream Port that supports Link speeds greater than > 5.0 GT/s, software must wait a minimum of 100 ms after Link training > completes before sending a Configuration Request to the device > immediately below that Port." > > Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com> > Reviewed-by: Mason Huo <mason.huo@starfivetech.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> > --- > drivers/pci/pci.h | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > index 5ecbcf041179..06f1f1eb878c 100644 > --- a/drivers/pci/pci.h > +++ b/drivers/pci/pci.h > @@ -22,6 +22,22 @@ > */ > #define PCIE_PME_TO_L2_TIMEOUT_US 10000 > > +/* > + * As described in PCI base specification r6.0, section 6.6.1 <Conventional > + * Reset>, there are two different use cases of the value: > + * > + * - "With a Downstream Port that does not support Link speeds greater > + * than 5.0 GT/s, software must wait a minimum of 100 ms following exit > + * from a Conventional Reset before sending a Configuration Request to > + * the device immediately below that Port." > + * > + * - "With a Downstream Port that supports Link speeds greater than > + * 5.0 GT/s, software must wait a minimum of 100 ms after Link training > + * completes before sending a Configuration Request to the device > + * immediately below that Port." > + */ > +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 > + > extern const unsigned char pcie_link_speed[]; > extern bool pci_early_dump; > > -- > 2.17.1 >
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 5ecbcf041179..06f1f1eb878c 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -22,6 +22,22 @@ */ #define PCIE_PME_TO_L2_TIMEOUT_US 10000 +/* + * As described in PCI base specification r6.0, section 6.6.1 <Conventional + * Reset>, there are two different use cases of the value: + * + * - "With a Downstream Port that does not support Link speeds greater + * than 5.0 GT/s, software must wait a minimum of 100 ms following exit + * from a Conventional Reset before sending a Configuration Request to + * the device immediately below that Port." + * + * - "With a Downstream Port that supports Link speeds greater than + * 5.0 GT/s, software must wait a minimum of 100 ms after Link training + * completes before sending a Configuration Request to the device + * immediately below that Port." + */ +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump;