| Message ID | 20231231034108.3262678-1-andersson@kernel.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | f3a4d7c3ffc3970e0f658711a2bb604d08999c0f |
| Headers | show |
| Series | [GIT,PULL] A few more Qualcomm Arm64 DeviceTree updates for v6.8 | expand |
Hello: This pull request was applied to soc/soc.git (for-next) by Arnd Bergmann <arnd@arndb.de>: On Sat, 30 Dec 2023 19:41:06 -0800 you wrote: > The following changes since commit b7b9a6aa7aea2bcba2d35d65e4ce2913115485a3: > > arm64: dts: qcom: sc8180x-primus: Allow UFS regulators load/mode setting (2023-12-17 14:28:17 -0600) > > are available in the Git repository at: > > https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/qcom-arm64-for-6.8-2 > > [...] Here is the summary with links: - [GIT,PULL] A few more Qualcomm Arm64 DeviceTree updates for v6.8 https://git.kernel.org/soc/soc/c/f3a4d7c3ffc3 You are awesome, thank you!
The following changes since commit b7b9a6aa7aea2bcba2d35d65e4ce2913115485a3: arm64: dts: qcom: sc8180x-primus: Allow UFS regulators load/mode setting (2023-12-17 14:28:17 -0600) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/qcom-arm64-for-6.8-2 for you to fetch changes up to 78403b37f6770441f80a78d13772394731afe055: arm64: dts: qcom: sc8180x: Fix up PCIe nodes (2023-12-20 06:26:30 -0600) ---------------------------------------------------------------- A few more Qualcomm Arm64 DeviceTree updates for v6.8 This corrects the rate of the UTMI clock on IPQ6018 USB0. The SDHCI controller on SC7280 gains missing markings for being cache-coherent. For SC8180X a typo in assignment of PCIe refgen clocks is corrected, PCI controllers are marked cache-coherent, and the USB SS PHY interrupts are corrected to allow wakeup. Similarly USB HS PHY and SS PHY interrupts are corrected to allow wakeup on SDM670. On SM8550 the X3 cluster idle state is properly described, and the latency numbers are adjusted for all the idle states. The PM8550 regulator supplies on X1E are corrected to match the driver and binding, and the timer node is updated to avoid an unnecessary validation error. ---------------------------------------------------------------- Abel Vesa (1): arm64: dts: qcom: x1e80100-qcp: Fix supplies for some LDOs in PM8550 Chukun Pan (1): arm64: dts: qcom: ipq6018: fix clock rates for GCC_USB0_MOCK_UTMI_CLK Johan Hovold (3): arm64: dts: qcom: sdm670: fix USB DP/DM HS PHY interrupts arm64: dts: qcom: sdm670: fix USB SS wakeup arm64: dts: qcom: sc8180x: fix USB SS wakeup Konrad Dybcio (5): arm64: dts: qcom: sc7280: Mark SDHCI hosts as cache-coherent arm64: dts: qcom: sm8550: Separate out X3 idle state arm64: dts: qcom: sm8550: Update idle state time requirements arm64: dts: qcom: sc8180x: Mark PCIe hosts cache-coherent arm64: dts: qcom: sc8180x: Fix up PCIe nodes Krzysztof Kozlowski (1): arm64: dts: qcom: x1e80100: align mem timer size cells with bindings arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sc8180x.dtsi | 14 +++++++++----- arch/arm64/boot/dts/qcom/sdm670.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm8550.dtsi | 32 ++++++++++++++++++++----------- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 4 +--- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 20 +++++++++---------- 7 files changed, 48 insertions(+), 34 deletions(-)