| Message ID | be3cbcae5c40fa72a52845d30dcc66c847a98cfa.1702616304.git.dsimic@manjaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3399 | expand |
Hello, Just checking, is there something preventing this patch from becoming accepted? I'd appreciate if you'd provide some feedback and let me know if there's something in the patch that needs adjusting. By the way, Stefan Nagy noted that he'll have this patch tested after the holidays. I guess that should help. On 2023-12-15 06:00, Dragan Simic wrote: > Add missing cache information to the Rockchip RK3399 SoC dtsi. The > specified > values were derived by hand from the cache size specifications > available from > the RK3399 datasheet; for future reference, here's a brief summary: > > - Each Cortex-A72 core has 48 KB of L1 instruction cache and > 32 KB of L1 data cache available, four-way set associative > - Each Cortex-A53 core core has 32 KB of instruction cache and > 32 KB of L1 data cache available, four-way set associative > - The big (A72) cluster has 1 MB of unified L2 cache available > - The little (A53) cluster has 512 KB of unified L2 cache available > > This patch allows /proc/cpuinfo and lscpu(1) to display proper RK3399 > cache > information, and it eliminates the following error in the kernel log: > > cacheinfo: Unable to detect cache hierarchy for CPU 0 > > While there, add a couple of somewhat useful comments, which may help a > bit > anyone going through the RK3399 SoC dtsi. > > Co-developed-by: Kyle Copperfield <kmcopper@danwin1210.me> > Signed-off-by: Dragan Simic <dsimic@manjaro.org> > --- > > Notes: > It's been a while since Kyle and I worked on this patch, and his > email > address seems to no longer work. Unfortunately, I have no idea is > there > some other email address that he actually uses now. However, Kyle > needs > to be mentioned as a co-author of this patch. > > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 64 +++++++++++++++++++++++- > 1 file changed, 62 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > index da0dfb237f85..f38c27f87cc9 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -41,22 +41,22 @@ cpus { > #size-cells = <0>; > > cpu-map { > - cluster0 { > + cluster0 { /* Cortex-A53 */ > core0 { > cpu = <&cpu_l0>; > }; > core1 { > cpu = <&cpu_l1>; > }; > core2 { > cpu = <&cpu_l2>; > }; > core3 { > cpu = <&cpu_l3>; > }; > }; > > - cluster1 { > + cluster1 { /* Cortex-A72 */ > core0 { > cpu = <&cpu_b0>; > }; > @@ -76,54 +76,89 @@ cpu_l0: cpu@0 { > #cooling-cells = <2>; /* min followed by max */ > dynamic-power-coefficient = <100>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache_l>; > }; > > cpu_l1: cpu@1 { > device_type = "cpu"; > compatible = "arm,cortex-a53"; > reg = <0x0 0x1>; > enable-method = "psci"; > capacity-dmips-mhz = <485>; > clocks = <&cru ARMCLKL>; > #cooling-cells = <2>; /* min followed by max */ > dynamic-power-coefficient = <100>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache_l>; > }; > > cpu_l2: cpu@2 { > device_type = "cpu"; > compatible = "arm,cortex-a53"; > reg = <0x0 0x2>; > enable-method = "psci"; > capacity-dmips-mhz = <485>; > clocks = <&cru ARMCLKL>; > #cooling-cells = <2>; /* min followed by max */ > dynamic-power-coefficient = <100>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache_l>; > }; > > cpu_l3: cpu@3 { > device_type = "cpu"; > compatible = "arm,cortex-a53"; > reg = <0x0 0x3>; > enable-method = "psci"; > capacity-dmips-mhz = <485>; > clocks = <&cru ARMCLKL>; > #cooling-cells = <2>; /* min followed by max */ > dynamic-power-coefficient = <100>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; > + i-cache-size = <0x8000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <128>; > + next-level-cache = <&l2_cache_l>; > }; > > cpu_b0: cpu@100 { > device_type = "cpu"; > compatible = "arm,cortex-a72"; > reg = <0x0 0x100>; > enable-method = "psci"; > capacity-dmips-mhz = <1024>; > clocks = <&cru ARMCLKB>; > #cooling-cells = <2>; /* min followed by max */ > dynamic-power-coefficient = <436>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2_cache_b>; > > thermal-idle { > #cooling-cells = <2>; > @@ -142,14 +177,39 @@ cpu_b1: cpu@101 { > #cooling-cells = <2>; /* min followed by max */ > dynamic-power-coefficient = <436>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; > + i-cache-size = <0xC000>; > + i-cache-line-size = <64>; > + i-cache-sets = <256>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <64>; > + d-cache-sets = <256>; > + next-level-cache = <&l2_cache_b>; > > thermal-idle { > #cooling-cells = <2>; > duration-us = <10000>; > exit-latency-us = <500>; > }; > }; > > + l2_cache_l: l2-cache-cluster0 { > + compatible = "cache"; > + cache-level = <2>; > + cache-unified; > + cache-size = <0x80000>; > + cache-line-size = <64>; > + cache-sets = <512>; > + }; > + > + l2_cache_b: l2-cache-cluster1 { > + compatible = "cache"; > + cache-level = <2>; > + cache-unified; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <1024>; > + }; > + > idle-states { > entry-method = "psci"; > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip
On 04/01/2024 09:50, Dragan Simic wrote: > Hello, > > Just checking, is there something preventing this patch from becoming > accepted? I'd appreciate if you'd provide some feedback and let me know > if there's something in the patch that needs adjusting. Merge window? Is it a fix? If not, the cutoff is around rc5-rc7, depending on your SoC maintainer preferences. Best regards, Krzysztof
On 2024-01-04 09:51, Krzysztof Kozlowski wrote: > On 04/01/2024 09:50, Dragan Simic wrote: >> Hello, >> >> Just checking, is there something preventing this patch from becoming >> accepted? I'd appreciate if you'd provide some feedback and let me >> know >> if there's something in the patch that needs adjusting. > > Merge window? Is it a fix? If not, the cutoff is around rc5-rc7, > depending on your SoC maintainer preferences. Ah, I see, thanks for the clarification. It isn't a bugfix, so I'll send the patch again during the next merge window.
Am Donnerstag, 4. Januar 2024, 09:55:35 CET schrieb Dragan Simic: > On 2024-01-04 09:51, Krzysztof Kozlowski wrote: > > On 04/01/2024 09:50, Dragan Simic wrote: > >> Hello, > >> > >> Just checking, is there something preventing this patch from becoming > >> accepted? I'd appreciate if you'd provide some feedback and let me > >> know > >> if there's something in the patch that needs adjusting. > > > > Merge window? Is it a fix? If not, the cutoff is around rc5-rc7, > > depending on your SoC maintainer preferences. > > Ah, I see, thanks for the clarification. It isn't a bugfix, so I'll > send the patch again during the next merge window. no need to resend. The main thing holding the patch back was xmas ;-) . But as Krzysztof wrote, the merge-window is upon us, so I'll pick this up for 6.9 . Thanks Heiko
On 2024-01-04 10:07, Heiko Stübner wrote: > Am Donnerstag, 4. Januar 2024, 09:55:35 CET schrieb Dragan Simic: >> On 2024-01-04 09:51, Krzysztof Kozlowski wrote: >> > On 04/01/2024 09:50, Dragan Simic wrote: >> >> Hello, >> >> >> >> Just checking, is there something preventing this patch from becoming >> >> accepted? I'd appreciate if you'd provide some feedback and let me >> >> know >> >> if there's something in the patch that needs adjusting. >> > >> > Merge window? Is it a fix? If not, the cutoff is around rc5-rc7, >> > depending on your SoC maintainer preferences. >> >> Ah, I see, thanks for the clarification. It isn't a bugfix, so I'll >> send the patch again during the next merge window. > > no need to resend. > > The main thing holding the patch back was xmas ;-) . > > But as Krzysztof wrote, the merge-window is upon us, so I'll pick this > up > for 6.9 . Awesome, thank you! :) I'll move forward and prepare a few more similar patches for other Rockchip SoCs, after I recover from some nasty flu I've unfortunately contracted.
On Fri, 15 Dec 2023 06:00:33 +0100, Dragan Simic wrote: > Add missing cache information to the Rockchip RK3399 SoC dtsi. The specified > values were derived by hand from the cache size specifications available from > the RK3399 datasheet; for future reference, here's a brief summary: > > - Each Cortex-A72 core has 48 KB of L1 instruction cache and > 32 KB of L1 data cache available, four-way set associative > - Each Cortex-A53 core core has 32 KB of instruction cache and > 32 KB of L1 data cache available, four-way set associative > - The big (A72) cluster has 1 MB of unified L2 cache available > - The little (A53) cluster has 512 KB of unified L2 cache available > > [...] Applied, thanks! [1/1] arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3399 commit: b72633ba5cfa932405832de25d0f0a11716903b4 Best regards,
On 2024-01-25 22:12, Heiko Stuebner wrote: > On Fri, 15 Dec 2023 06:00:33 +0100, Dragan Simic wrote: >> Add missing cache information to the Rockchip RK3399 SoC dtsi. The >> specified >> values were derived by hand from the cache size specifications >> available from >> the RK3399 datasheet; for future reference, here's a brief summary: >> >> - Each Cortex-A72 core has 48 KB of L1 instruction cache and >> 32 KB of L1 data cache available, four-way set associative >> - Each Cortex-A53 core core has 32 KB of instruction cache and >> 32 KB of L1 data cache available, four-way set associative >> - The big (A72) cluster has 1 MB of unified L2 cache available >> - The little (A53) cluster has 512 KB of unified L2 cache available >> >> [...] > > Applied, thanks! > > [1/1] arm64: dts: rockchip: Add cache information to the SoC dtsi for > RK3399 > commit: b72633ba5cfa932405832de25d0f0a11716903b4 Great, thank you!
Hello Heiko, On 2024-01-04 10:12, Dragan Simic wrote: > On 2024-01-04 10:07, Heiko Stübner wrote: >> Am Donnerstag, 4. Januar 2024, 09:55:35 CET schrieb Dragan Simic: >>> On 2024-01-04 09:51, Krzysztof Kozlowski wrote: >>> > On 04/01/2024 09:50, Dragan Simic wrote: >>> >> Just checking, is there something preventing this patch from becoming >>> >> accepted? I'd appreciate if you'd provide some feedback and let me >>> >> know if there's something in the patch that needs adjusting. >>> > >>> > Merge window? Is it a fix? If not, the cutoff is around rc5-rc7, >>> > depending on your SoC maintainer preferences. >>> >>> Ah, I see, thanks for the clarification. It isn't a bugfix, so I'll >>> send the patch again during the next merge window. >> >> no need to resend. >> >> The main thing holding the patch back was xmas ;-) . >> >> But as Krzysztof wrote, the merge-window is upon us, so I'll pick this >> up >> for 6.9 . > > Awesome, thank you! :) I'll move forward and prepare a few more > similar patches for other Rockchip SoCs, after I recover from some > nasty flu I've unfortunately contracted. It took me a while, but pretty much the same patches for the RK3328 [1] and the RK356x [2] are now on the mailing list. Please, have a look. [1] https://lore.kernel.org/linux-rockchip/e61173d87f5f41af80e6f87f8820ce8d06f7c20c.1709491127.git.dsimic@manjaro.org/ [2] https://lore.kernel.org/linux-rockchip/2285ee41e165813011220f9469e28697923aa6e0.1709491108.git.dsimic@manjaro.org/
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index da0dfb237f85..f38c27f87cc9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -41,22 +41,22 @@ cpus { #size-cells = <0>; cpu-map { - cluster0 { + cluster0 { /* Cortex-A53 */ core0 { cpu = <&cpu_l0>; }; core1 { cpu = <&cpu_l1>; }; core2 { cpu = <&cpu_l2>; }; core3 { cpu = <&cpu_l3>; }; }; - cluster1 { + cluster1 { /* Cortex-A72 */ core0 { cpu = <&cpu_b0>; }; @@ -76,54 +76,89 @@ cpu_l0: cpu@0 { #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; capacity-dmips-mhz = <485>; clocks = <&cru ARMCLKL>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; capacity-dmips-mhz = <485>; clocks = <&cru ARMCLKL>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; capacity-dmips-mhz = <485>; clocks = <&cru ARMCLKL>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_b0: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&cru ARMCLKB>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b>; thermal-idle { #cooling-cells = <2>; @@ -142,14 +177,39 @@ cpu_b1: cpu@101 { #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + i-cache-size = <0xC000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b>; thermal-idle { #cooling-cells = <2>; duration-us = <10000>; exit-latency-us = <500>; }; }; + l2_cache_l: l2-cache-cluster0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; + + l2_cache_b: l2-cache-cluster1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; + }; + idle-states { entry-method = "psci";
Add missing cache information to the Rockchip RK3399 SoC dtsi. The specified values were derived by hand from the cache size specifications available from the RK3399 datasheet; for future reference, here's a brief summary: - Each Cortex-A72 core has 48 KB of L1 instruction cache and 32 KB of L1 data cache available, four-way set associative - Each Cortex-A53 core core has 32 KB of instruction cache and 32 KB of L1 data cache available, four-way set associative - The big (A72) cluster has 1 MB of unified L2 cache available - The little (A53) cluster has 512 KB of unified L2 cache available This patch allows /proc/cpuinfo and lscpu(1) to display proper RK3399 cache information, and it eliminates the following error in the kernel log: cacheinfo: Unable to detect cache hierarchy for CPU 0 While there, add a couple of somewhat useful comments, which may help a bit anyone going through the RK3399 SoC dtsi. Co-developed-by: Kyle Copperfield <kmcopper@danwin1210.me> Signed-off-by: Dragan Simic <dsimic@manjaro.org> --- Notes: It's been a while since Kyle and I worked on this patch, and his email address seems to no longer work. Unfortunately, I have no idea is there some other email address that he actually uses now. However, Kyle needs to be mentioned as a co-author of this patch. arch/arm64/boot/dts/rockchip/rk3399.dtsi | 64 +++++++++++++++++++++++- 1 file changed, 62 insertions(+), 2 deletions(-)