diff mbox series

[net-next,3/3] net/mlx5: DPLL, Implement fractional frequency offset get pin op

Message ID 20240103132838.1501801-4-jiri@resnulli.us (mailing list archive)
State Accepted
Commit f035dca34ede00d667a3e2d16e1c731161eeacec
Delegated to: Netdev Maintainers
Headers show
Series dpll: expose fractional frequency offset value to user | expand

Checks

Context Check Description
netdev/series_format success Posting correctly formatted
netdev/tree_selection success Clearly marked for net-next
netdev/ynl success Generated files up to date; no warnings/errors; no diff in generated;
netdev/fixes_present success Fixes tag not required for -next series
netdev/header_inline success No static functions without inline keyword in header files
netdev/build_32bit success Errors and warnings before: 1113 this patch: 1113
netdev/cc_maintainers warning 1 maintainers not CCed: linux-rdma@vger.kernel.org
netdev/build_clang success Errors and warnings before: 1140 this patch: 1140
netdev/verify_signedoff success Signed-off-by tag matches author and committer
netdev/deprecated_api success None detected
netdev/check_selftest success No net selftest shell script
netdev/verify_fixes success No Fixes tag
netdev/build_allmodconfig_warn success Errors and warnings before: 1140 this patch: 1140
netdev/checkpatch warning WARNING: line length of 86 exceeds 80 columns
netdev/build_clang_rust success No Rust files in patch. Skipping build
netdev/kdoc success Errors and warnings before: 0 this patch: 0
netdev/source_inline success Was 0 now: 0

Commit Message

Jiri Pirko Jan. 3, 2024, 1:28 p.m. UTC 
From: Jiri Pirko <jiri@nvidia.com>

Implement ffo_get() pin op filling it up to MSEED.frequency_diff value.

Signed-off-by: Jiri Pirko <jiri@nvidia.com>
---
 .../net/ethernet/mellanox/mlx5/core/dpll.c    | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

Comments

Arkadiusz Kubalewski Jan. 5, 2024, 1:32 p.m. UTC | #1 
>From: Jiri Pirko <jiri@resnulli.us>
>Sent: Wednesday, January 3, 2024 2:29 PM
>
>From: Jiri Pirko <jiri@nvidia.com>
>
>Implement ffo_get() pin op filling it up to MSEED.frequency_diff value.
>
>Signed-off-by: Jiri Pirko <jiri@nvidia.com>
>---
> .../net/ethernet/mellanox/mlx5/core/dpll.c    | 31 +++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
>diff --git a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c
>b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c
>index dbe09d2f2069..18fed2b34fb1 100644
>--- a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c
>+++ b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c
>@@ -40,6 +40,8 @@ struct mlx5_dpll_synce_status {
> 	enum mlx5_msees_admin_status admin_status;
> 	enum mlx5_msees_oper_status oper_status;
> 	bool ho_acq;
>+	bool oper_freq_measure;
>+	s32 frequency_diff;
> };
>
> static int
>@@ -57,6 +59,8 @@ mlx5_dpll_synce_status_get(struct mlx5_core_dev *mdev,
> 	synce_status->admin_status = MLX5_GET(msees_reg, out, admin_status);
> 	synce_status->oper_status = MLX5_GET(msees_reg, out, oper_status);
> 	synce_status->ho_acq = MLX5_GET(msees_reg, out, ho_acq);
>+	synce_status->oper_freq_measure = MLX5_GET(msees_reg, out,
>oper_freq_measure);
>+	synce_status->frequency_diff = MLX5_GET(msees_reg, out,
>frequency_diff);
> 	return 0;
> }
>
>@@ -69,8 +73,10 @@ mlx5_dpll_synce_status_set(struct mlx5_core_dev *mdev,
>
> 	MLX5_SET(msees_reg, in, field_select,
> 		 MLX5_MSEES_FIELD_SELECT_ENABLE |
>+		 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE |
> 		 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS);
> 	MLX5_SET(msees_reg, in, admin_status, admin_status);
>+	MLX5_SET(msees_reg, in, admin_freq_measure, true);
> 	return mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out),
> 				    MLX5_REG_MSEES, 0, 1);
> }
>@@ -102,6 +108,16 @@ mlx5_dpll_pin_state_get(struct mlx5_dpll_synce_status
>*synce_status)
> 	       DPLL_PIN_STATE_CONNECTED : DPLL_PIN_STATE_DISCONNECTED;
> }
>
>+static int
>+mlx5_dpll_pin_ffo_get(struct mlx5_dpll_synce_status *synce_status,
>+		      s64 *ffo)
>+{
>+	if (!synce_status->oper_freq_measure)
>+		return -ENODATA;
>+	*ffo = synce_status->frequency_diff;
>+	return 0;
>+}
>+
> static int mlx5_dpll_device_lock_status_get(const struct dpll_device
>*dpll,
> 					    void *priv,
> 					    enum dpll_lock_status *status,
>@@ -175,10 +191,25 @@ static int mlx5_dpll_state_on_dpll_set(const struct
>dpll_pin *pin,
> 					  MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING);
> }
>
>+static int mlx5_dpll_ffo_get(const struct dpll_pin *pin, void *pin_priv,
>+			     const struct dpll_device *dpll, void *dpll_priv,
>+			     s64 *ffo, struct netlink_ext_ack *extack)
>+{
>+	struct mlx5_dpll_synce_status synce_status;
>+	struct mlx5_dpll *mdpll = pin_priv;
>+	int err;
>+
>+	err = mlx5_dpll_synce_status_get(mdpll->mdev, &synce_status);
>+	if (err)
>+		return err;
>+	return mlx5_dpll_pin_ffo_get(&synce_status, ffo);
>+}
>+
> static const struct dpll_pin_ops mlx5_dpll_pins_ops = {
> 	.direction_get = mlx5_dpll_pin_direction_get,
> 	.state_on_dpll_get = mlx5_dpll_state_on_dpll_get,
> 	.state_on_dpll_set = mlx5_dpll_state_on_dpll_set,
>+	.ffo_get = mlx5_dpll_ffo_get,
> };
>
> static const struct dpll_pin_properties mlx5_dpll_pin_properties = {
>--
>2.43.0

Hi Jiri,

Looks good to me.

Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
diff mbox series

Patch

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c
index dbe09d2f2069..18fed2b34fb1 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/dpll.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/dpll.c
@@ -40,6 +40,8 @@  struct mlx5_dpll_synce_status {
 	enum mlx5_msees_admin_status admin_status;
 	enum mlx5_msees_oper_status oper_status;
 	bool ho_acq;
+	bool oper_freq_measure;
+	s32 frequency_diff;
 };
 
 static int
@@ -57,6 +59,8 @@  mlx5_dpll_synce_status_get(struct mlx5_core_dev *mdev,
 	synce_status->admin_status = MLX5_GET(msees_reg, out, admin_status);
 	synce_status->oper_status = MLX5_GET(msees_reg, out, oper_status);
 	synce_status->ho_acq = MLX5_GET(msees_reg, out, ho_acq);
+	synce_status->oper_freq_measure = MLX5_GET(msees_reg, out, oper_freq_measure);
+	synce_status->frequency_diff = MLX5_GET(msees_reg, out, frequency_diff);
 	return 0;
 }
 
@@ -69,8 +73,10 @@  mlx5_dpll_synce_status_set(struct mlx5_core_dev *mdev,
 
 	MLX5_SET(msees_reg, in, field_select,
 		 MLX5_MSEES_FIELD_SELECT_ENABLE |
+		 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE |
 		 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS);
 	MLX5_SET(msees_reg, in, admin_status, admin_status);
+	MLX5_SET(msees_reg, in, admin_freq_measure, true);
 	return mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out),
 				    MLX5_REG_MSEES, 0, 1);
 }
@@ -102,6 +108,16 @@  mlx5_dpll_pin_state_get(struct mlx5_dpll_synce_status *synce_status)
 	       DPLL_PIN_STATE_CONNECTED : DPLL_PIN_STATE_DISCONNECTED;
 }
 
+static int
+mlx5_dpll_pin_ffo_get(struct mlx5_dpll_synce_status *synce_status,
+		      s64 *ffo)
+{
+	if (!synce_status->oper_freq_measure)
+		return -ENODATA;
+	*ffo = synce_status->frequency_diff;
+	return 0;
+}
+
 static int mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll,
 					    void *priv,
 					    enum dpll_lock_status *status,
@@ -175,10 +191,25 @@  static int mlx5_dpll_state_on_dpll_set(const struct dpll_pin *pin,
 					  MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING);
 }
 
+static int mlx5_dpll_ffo_get(const struct dpll_pin *pin, void *pin_priv,
+			     const struct dpll_device *dpll, void *dpll_priv,
+			     s64 *ffo, struct netlink_ext_ack *extack)
+{
+	struct mlx5_dpll_synce_status synce_status;
+	struct mlx5_dpll *mdpll = pin_priv;
+	int err;
+
+	err = mlx5_dpll_synce_status_get(mdpll->mdev, &synce_status);
+	if (err)
+		return err;
+	return mlx5_dpll_pin_ffo_get(&synce_status, ffo);
+}
+
 static const struct dpll_pin_ops mlx5_dpll_pins_ops = {
 	.direction_get = mlx5_dpll_pin_direction_get,
 	.state_on_dpll_get = mlx5_dpll_state_on_dpll_get,
 	.state_on_dpll_set = mlx5_dpll_state_on_dpll_set,
+	.ffo_get = mlx5_dpll_ffo_get,
 };
 
 static const struct dpll_pin_properties mlx5_dpll_pin_properties = {