| Message ID | 20240108120725.20057-4-stanislav.lisovskiy@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Bigjoiner refactoring | expand |
On Mon, Jan 08, 2024 at 02:07:25PM +0200, Stanislav Lisovskiy wrote: > Handle only bigjoiner masters in skl_commit_modeset_enables/disables, > slave crtcs should be handled by master hooks. Same for encoders. > That way we can also remove a bunch of checks like intel_crtc_is_bigjoiner_slave. > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 3 +- > drivers/gpu/drm/i915/display/intel_display.c | 148 ++++++++++++++++--- > 2 files changed, 128 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 2746655bcb264..9723f1b49cf95 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3340,8 +3340,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state, > { > drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); > > - if (!intel_crtc_is_bigjoiner_slave(crtc_state)) > - intel_ddi_enable_transcoder_func(encoder, crtc_state); > + intel_ddi_enable_transcoder_func(encoder, crtc_state); > > /* Enable/Disable DP2.0 SDP split config before transcoder */ > intel_audio_sdp_split_update(crtc_state); > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index eec76ec167069..24388226db465 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -1630,6 +1630,93 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta > hsw_set_transconf(crtc_state); > } > > +static void hsw_crtc_enable_slave(struct intel_atomic_state *state, > + struct intel_crtc *crtc) > +{ > + const struct intel_crtc_state *new_crtc_state = > + intel_atomic_get_new_crtc_state(state, crtc); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + enum pipe pipe = crtc->pipe, hsw_workaround_pipe; > + bool psl_clkgate_wa; > + > + if (drm_WARN_ON(&dev_priv->drm, crtc->active)) > + return; > + > + intel_dmc_enable_pipe(dev_priv, crtc->pipe); > + > + if (!new_crtc_state->bigjoiner_pipes) { > + intel_encoders_pre_pll_enable(state, crtc); > + > + if (new_crtc_state->shared_dpll) > + intel_enable_shared_dpll(new_crtc_state); > + > + intel_encoders_pre_enable(state, crtc); > + } else { > + icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); > + } > + > + intel_dsc_enable(new_crtc_state); > + > + if (DISPLAY_VER(dev_priv) >= 13) > + intel_uncompressed_joiner_enable(new_crtc_state); > + > + intel_set_pipe_src_size(new_crtc_state); > + if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) > + bdw_set_pipe_misc(new_crtc_state); > + > + crtc->active = true; > + > + /* Display WA #1180: WaDisableScalarClockGating: glk */ > + psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && > + new_crtc_state->pch_pfit.enabled; > + if (psl_clkgate_wa) > + glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); > + > + if (DISPLAY_VER(dev_priv) >= 9) > + skl_pfit_enable(new_crtc_state); > + else > + ilk_pfit_enable(new_crtc_state); > + > + /* > + * On ILK+ LUT must be loaded before the pipe is running but with > + * clocks enabled > + */ > + intel_color_load_luts(new_crtc_state); > + intel_color_commit_noarm(new_crtc_state); > + intel_color_commit_arm(new_crtc_state); > + /* update DSPCNTR to configure gamma/csc for pipe bottom color */ > + if (DISPLAY_VER(dev_priv) < 9) > + intel_disable_primary_plane(new_crtc_state); > + > + hsw_set_linetime_wm(new_crtc_state); > + > + if (DISPLAY_VER(dev_priv) >= 11) > + icl_set_pipe_chicken(new_crtc_state); > + > + intel_initial_watermarks(state, crtc); > + > + intel_crtc_vblank_on(new_crtc_state); > + > + intel_encoders_enable(state, crtc); > + > + if (psl_clkgate_wa) { > + intel_crtc_wait_for_next_vblank(crtc); > + glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); > + } > + > + /* If we change the relative order between pipe/planes enabling, we need > + * to change the workaround. */ > + hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; > + if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { > + struct intel_crtc *wa_crtc; > + > + wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); > + > + intel_crtc_wait_for_next_vblank(wa_crtc); > + intel_crtc_wait_for_next_vblank(wa_crtc); > + } > +} > + > static void hsw_crtc_enable(struct intel_atomic_state *state, > struct intel_crtc *crtc) > { > @@ -1639,10 +1726,16 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, > enum pipe pipe = crtc->pipe, hsw_workaround_pipe; > enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; > bool psl_clkgate_wa; > + struct intel_crtc *slave_crtc; > > if (drm_WARN_ON(&dev_priv->drm, crtc->active)) > return; > > + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, > + intel_crtc_bigjoiner_slave_pipes(new_crtc_state)) { > + hsw_crtc_enable_slave(state, slave_crtc); > + } Thats not really what I'm after. Ideally we shouldn't end up with any master vs. slave split here, just a pipe vs. transcoder split. And then the high level flow should look something along the lines of: crtc_enable() { transcoder_thing1(); for_each_joined_pipe() pipe_thing1(); transcoder_thing2(); for_each_joined_pipe() pipe_thing2(); ... }
On Fri, Jan 12, 2024 at 06:47:10PM +0200, Ville Syrjälä wrote: > On Mon, Jan 08, 2024 at 02:07:25PM +0200, Stanislav Lisovskiy wrote: > > Handle only bigjoiner masters in skl_commit_modeset_enables/disables, > > slave crtcs should be handled by master hooks. Same for encoders. > > That way we can also remove a bunch of checks like intel_crtc_is_bigjoiner_slave. > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 3 +- > > drivers/gpu/drm/i915/display/intel_display.c | 148 ++++++++++++++++--- > > 2 files changed, 128 insertions(+), 23 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 2746655bcb264..9723f1b49cf95 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -3340,8 +3340,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state, > > { > > drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); > > > > - if (!intel_crtc_is_bigjoiner_slave(crtc_state)) > > - intel_ddi_enable_transcoder_func(encoder, crtc_state); > > + intel_ddi_enable_transcoder_func(encoder, crtc_state); > > > > /* Enable/Disable DP2.0 SDP split config before transcoder */ > > intel_audio_sdp_split_update(crtc_state); > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index eec76ec167069..24388226db465 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -1630,6 +1630,93 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta > > hsw_set_transconf(crtc_state); > > } > > > > +static void hsw_crtc_enable_slave(struct intel_atomic_state *state, > > + struct intel_crtc *crtc) > > +{ > > + const struct intel_crtc_state *new_crtc_state = > > + intel_atomic_get_new_crtc_state(state, crtc); > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > + enum pipe pipe = crtc->pipe, hsw_workaround_pipe; > > + bool psl_clkgate_wa; > > + > > + if (drm_WARN_ON(&dev_priv->drm, crtc->active)) > > + return; > > + > > + intel_dmc_enable_pipe(dev_priv, crtc->pipe); > > + > > + if (!new_crtc_state->bigjoiner_pipes) { > > + intel_encoders_pre_pll_enable(state, crtc); > > + > > + if (new_crtc_state->shared_dpll) > > + intel_enable_shared_dpll(new_crtc_state); > > + > > + intel_encoders_pre_enable(state, crtc); > > + } else { > > + icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); > > + } > > + > > + intel_dsc_enable(new_crtc_state); > > + > > + if (DISPLAY_VER(dev_priv) >= 13) > > + intel_uncompressed_joiner_enable(new_crtc_state); > > + > > + intel_set_pipe_src_size(new_crtc_state); > > + if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) > > + bdw_set_pipe_misc(new_crtc_state); > > + > > + crtc->active = true; > > + > > + /* Display WA #1180: WaDisableScalarClockGating: glk */ > > + psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && > > + new_crtc_state->pch_pfit.enabled; > > + if (psl_clkgate_wa) > > + glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); > > + > > + if (DISPLAY_VER(dev_priv) >= 9) > > + skl_pfit_enable(new_crtc_state); > > + else > > + ilk_pfit_enable(new_crtc_state); > > + > > + /* > > + * On ILK+ LUT must be loaded before the pipe is running but with > > + * clocks enabled > > + */ > > + intel_color_load_luts(new_crtc_state); > > + intel_color_commit_noarm(new_crtc_state); > > + intel_color_commit_arm(new_crtc_state); > > + /* update DSPCNTR to configure gamma/csc for pipe bottom color */ > > + if (DISPLAY_VER(dev_priv) < 9) > > + intel_disable_primary_plane(new_crtc_state); > > + > > + hsw_set_linetime_wm(new_crtc_state); > > + > > + if (DISPLAY_VER(dev_priv) >= 11) > > + icl_set_pipe_chicken(new_crtc_state); > > + > > + intel_initial_watermarks(state, crtc); > > + > > + intel_crtc_vblank_on(new_crtc_state); > > + > > + intel_encoders_enable(state, crtc); > > + > > + if (psl_clkgate_wa) { > > + intel_crtc_wait_for_next_vblank(crtc); > > + glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); > > + } > > + > > + /* If we change the relative order between pipe/planes enabling, we need > > + * to change the workaround. */ > > + hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; > > + if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { > > + struct intel_crtc *wa_crtc; > > + > > + wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); > > + > > + intel_crtc_wait_for_next_vblank(wa_crtc); > > + intel_crtc_wait_for_next_vblank(wa_crtc); > > + } > > +} > > + > > static void hsw_crtc_enable(struct intel_atomic_state *state, > > struct intel_crtc *crtc) > > { > > @@ -1639,10 +1726,16 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, > > enum pipe pipe = crtc->pipe, hsw_workaround_pipe; > > enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; > > bool psl_clkgate_wa; > > + struct intel_crtc *slave_crtc; > > > > if (drm_WARN_ON(&dev_priv->drm, crtc->active)) > > return; > > > > + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, > > + intel_crtc_bigjoiner_slave_pipes(new_crtc_state)) { > > + hsw_crtc_enable_slave(state, slave_crtc); > > + } > > Thats not really what I'm after. Ideally we shouldn't end up with > any master vs. slave split here, just a pipe vs. transcoder split. > And then the high level flow should look something along the > lines of: > > crtc_enable() > { > transcoder_thing1(); > > for_each_joined_pipe() > pipe_thing1(); > > transcoder_thing2(); > > for_each_joined_pipe() > pipe_thing2(); > > ... > } > > -- > Ville Syrjälä Yes, I remember we discussed that you don't want any slaves to be processed in *commit_modeset_enables/disables, I guess it obivously means we need to process the here. Ah, I guess you mean we don't explicitly state, those are slaves but just iterate through all joined pipe mask. Okay, got it(wonder why I didn't do that myself initially..) Stan > Intel
On Fri, Jan 12, 2024 at 06:47:10PM +0200, Ville Syrjälä wrote: > On Mon, Jan 08, 2024 at 02:07:25PM +0200, Stanislav Lisovskiy wrote: > > Handle only bigjoiner masters in skl_commit_modeset_enables/disables, > > slave crtcs should be handled by master hooks. Same for encoders. > > That way we can also remove a bunch of checks like intel_crtc_is_bigjoiner_slave. > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 3 +- > > drivers/gpu/drm/i915/display/intel_display.c | 148 ++++++++++++++++--- > > 2 files changed, 128 insertions(+), 23 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > > index 2746655bcb264..9723f1b49cf95 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -3340,8 +3340,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state, > > { > > drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); > > > > - if (!intel_crtc_is_bigjoiner_slave(crtc_state)) > > - intel_ddi_enable_transcoder_func(encoder, crtc_state); > > + intel_ddi_enable_transcoder_func(encoder, crtc_state); > > > > /* Enable/Disable DP2.0 SDP split config before transcoder */ > > intel_audio_sdp_split_update(crtc_state); > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index eec76ec167069..24388226db465 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -1630,6 +1630,93 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta > > hsw_set_transconf(crtc_state); > > } > > > > +static void hsw_crtc_enable_slave(struct intel_atomic_state *state, > > + struct intel_crtc *crtc) > > +{ > > + const struct intel_crtc_state *new_crtc_state = > > + intel_atomic_get_new_crtc_state(state, crtc); > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > + enum pipe pipe = crtc->pipe, hsw_workaround_pipe; > > + bool psl_clkgate_wa; > > + > > + if (drm_WARN_ON(&dev_priv->drm, crtc->active)) > > + return; > > + > > + intel_dmc_enable_pipe(dev_priv, crtc->pipe); > > + > > + if (!new_crtc_state->bigjoiner_pipes) { > > + intel_encoders_pre_pll_enable(state, crtc); > > + > > + if (new_crtc_state->shared_dpll) > > + intel_enable_shared_dpll(new_crtc_state); > > + > > + intel_encoders_pre_enable(state, crtc); > > + } else { > > + icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); > > + } > > + > > + intel_dsc_enable(new_crtc_state); > > + > > + if (DISPLAY_VER(dev_priv) >= 13) > > + intel_uncompressed_joiner_enable(new_crtc_state); > > + > > + intel_set_pipe_src_size(new_crtc_state); > > + if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) > > + bdw_set_pipe_misc(new_crtc_state); > > + > > + crtc->active = true; > > + > > + /* Display WA #1180: WaDisableScalarClockGating: glk */ > > + psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && > > + new_crtc_state->pch_pfit.enabled; > > + if (psl_clkgate_wa) > > + glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); > > + > > + if (DISPLAY_VER(dev_priv) >= 9) > > + skl_pfit_enable(new_crtc_state); > > + else > > + ilk_pfit_enable(new_crtc_state); > > + > > + /* > > + * On ILK+ LUT must be loaded before the pipe is running but with > > + * clocks enabled > > + */ > > + intel_color_load_luts(new_crtc_state); > > + intel_color_commit_noarm(new_crtc_state); > > + intel_color_commit_arm(new_crtc_state); > > + /* update DSPCNTR to configure gamma/csc for pipe bottom color */ > > + if (DISPLAY_VER(dev_priv) < 9) > > + intel_disable_primary_plane(new_crtc_state); > > + > > + hsw_set_linetime_wm(new_crtc_state); > > + > > + if (DISPLAY_VER(dev_priv) >= 11) > > + icl_set_pipe_chicken(new_crtc_state); > > + > > + intel_initial_watermarks(state, crtc); > > + > > + intel_crtc_vblank_on(new_crtc_state); > > + > > + intel_encoders_enable(state, crtc); > > + > > + if (psl_clkgate_wa) { > > + intel_crtc_wait_for_next_vblank(crtc); > > + glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); > > + } > > + > > + /* If we change the relative order between pipe/planes enabling, we need > > + * to change the workaround. */ > > + hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; > > + if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { > > + struct intel_crtc *wa_crtc; > > + > > + wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); > > + > > + intel_crtc_wait_for_next_vblank(wa_crtc); > > + intel_crtc_wait_for_next_vblank(wa_crtc); > > + } > > +} > > + > > static void hsw_crtc_enable(struct intel_atomic_state *state, > > struct intel_crtc *crtc) > > { > > @@ -1639,10 +1726,16 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, > > enum pipe pipe = crtc->pipe, hsw_workaround_pipe; > > enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; > > bool psl_clkgate_wa; > > + struct intel_crtc *slave_crtc; > > > > if (drm_WARN_ON(&dev_priv->drm, crtc->active)) > > return; > > > > + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, > > + intel_crtc_bigjoiner_slave_pipes(new_crtc_state)) { > > + hsw_crtc_enable_slave(state, slave_crtc); > > + } > > Thats not really what I'm after. Ideally we shouldn't end up with > any master vs. slave split here, just a pipe vs. transcoder split. > And then the high level flow should look something along the > lines of: > > crtc_enable() > { > transcoder_thing1(); > > for_each_joined_pipe() > pipe_thing1(); One more thing. We can just iterate through joined pipe mask here, since BSpec dictates different order how master/slave should be configured, based on whether we are enabling or disabling, i.e for enabling we first enable slave pipes, then master, for disabling we do vice versa. Wondering then - should we invent somekind of a special macro for this? Stan > > transcoder_thing2(); > > for_each_joined_pipe() > pipe_thing2(); > > ... > } > > -- > Ville Syrjälä > Intel
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 2746655bcb264..9723f1b49cf95 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3340,8 +3340,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state, { drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); - if (!intel_crtc_is_bigjoiner_slave(crtc_state)) - intel_ddi_enable_transcoder_func(encoder, crtc_state); + intel_ddi_enable_transcoder_func(encoder, crtc_state); /* Enable/Disable DP2.0 SDP split config before transcoder */ intel_audio_sdp_split_update(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index eec76ec167069..24388226db465 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1630,6 +1630,93 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta hsw_set_transconf(crtc_state); } +static void hsw_crtc_enable_slave(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe, hsw_workaround_pipe; + bool psl_clkgate_wa; + + if (drm_WARN_ON(&dev_priv->drm, crtc->active)) + return; + + intel_dmc_enable_pipe(dev_priv, crtc->pipe); + + if (!new_crtc_state->bigjoiner_pipes) { + intel_encoders_pre_pll_enable(state, crtc); + + if (new_crtc_state->shared_dpll) + intel_enable_shared_dpll(new_crtc_state); + + intel_encoders_pre_enable(state, crtc); + } else { + icl_ddi_bigjoiner_pre_enable(state, new_crtc_state); + } + + intel_dsc_enable(new_crtc_state); + + if (DISPLAY_VER(dev_priv) >= 13) + intel_uncompressed_joiner_enable(new_crtc_state); + + intel_set_pipe_src_size(new_crtc_state); + if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) + bdw_set_pipe_misc(new_crtc_state); + + crtc->active = true; + + /* Display WA #1180: WaDisableScalarClockGating: glk */ + psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 && + new_crtc_state->pch_pfit.enabled; + if (psl_clkgate_wa) + glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); + + if (DISPLAY_VER(dev_priv) >= 9) + skl_pfit_enable(new_crtc_state); + else + ilk_pfit_enable(new_crtc_state); + + /* + * On ILK+ LUT must be loaded before the pipe is running but with + * clocks enabled + */ + intel_color_load_luts(new_crtc_state); + intel_color_commit_noarm(new_crtc_state); + intel_color_commit_arm(new_crtc_state); + /* update DSPCNTR to configure gamma/csc for pipe bottom color */ + if (DISPLAY_VER(dev_priv) < 9) + intel_disable_primary_plane(new_crtc_state); + + hsw_set_linetime_wm(new_crtc_state); + + if (DISPLAY_VER(dev_priv) >= 11) + icl_set_pipe_chicken(new_crtc_state); + + intel_initial_watermarks(state, crtc); + + intel_crtc_vblank_on(new_crtc_state); + + intel_encoders_enable(state, crtc); + + if (psl_clkgate_wa) { + intel_crtc_wait_for_next_vblank(crtc); + glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false); + } + + /* If we change the relative order between pipe/planes enabling, we need + * to change the workaround. */ + hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; + if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { + struct intel_crtc *wa_crtc; + + wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe); + + intel_crtc_wait_for_next_vblank(wa_crtc); + intel_crtc_wait_for_next_vblank(wa_crtc); + } +} + static void hsw_crtc_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -1639,10 +1726,16 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, enum pipe pipe = crtc->pipe, hsw_workaround_pipe; enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; bool psl_clkgate_wa; + struct intel_crtc *slave_crtc; if (drm_WARN_ON(&dev_priv->drm, crtc->active)) return; + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc, + intel_crtc_bigjoiner_slave_pipes(new_crtc_state)) { + hsw_crtc_enable_slave(state, slave_crtc); + } + intel_dmc_enable_pipe(dev_priv, crtc->pipe); if (!new_crtc_state->bigjoiner_pipes) { @@ -1665,8 +1758,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) bdw_set_pipe_misc(new_crtc_state); - if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) && - !transcoder_is_dsi(cpu_transcoder)) + if (!transcoder_is_dsi(cpu_transcoder)) hsw_configure_cpu_transcoder(new_crtc_state); crtc->active = true; @@ -1700,9 +1792,6 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_initial_watermarks(state, crtc); - if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) - intel_crtc_vblank_on(new_crtc_state); - intel_encoders_enable(state, crtc); if (psl_clkgate_wa) { @@ -1777,6 +1866,15 @@ static void ilk_crtc_disable(struct intel_atomic_state *state, intel_disable_shared_dpll(old_crtc_state); } +static void hsw_crtc_disable_slave(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + + intel_disable_shared_dpll(old_crtc_state); +} + static void hsw_crtc_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -1788,23 +1886,21 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, * FIXME collapse everything to one hook. * Need care with mst->ddi interactions. */ - if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { - intel_encoders_disable(state, crtc); - intel_encoders_post_disable(state, crtc); - } + intel_encoders_disable(state, crtc); + intel_encoders_post_disable(state, crtc); intel_disable_shared_dpll(old_crtc_state); - if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) { - struct intel_crtc *slave_crtc; + struct intel_crtc *slave_crtc; - intel_encoders_post_pll_disable(state, crtc); + intel_encoders_post_pll_disable(state, crtc); - intel_dmc_disable_pipe(i915, crtc->pipe); + intel_dmc_disable_pipe(i915, crtc->pipe); - for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, - intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) - intel_dmc_disable_pipe(i915, slave_crtc->pipe); + for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, + intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) { + intel_dmc_disable_pipe(i915, slave_crtc->pipe); + hsw_crtc_disable_slave(state, slave_crtc); } } @@ -6791,8 +6887,10 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) * Slave vblanks are masked till Master Vblanks. */ if (!is_trans_port_sync_slave(old_crtc_state) && - !intel_dp_mst_is_slave_trans(old_crtc_state) && - !intel_crtc_is_bigjoiner_slave(old_crtc_state)) + !intel_dp_mst_is_slave_trans(old_crtc_state)) + continue; + + if (intel_crtc_is_bigjoiner_slave(old_crtc_state)) continue; intel_old_crtc_state_disables(state, old_crtc_state, @@ -6810,6 +6908,9 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) if (!old_crtc_state->hw.active) continue; + if (intel_crtc_is_bigjoiner_slave(old_crtc_state)) + continue; + intel_old_crtc_state_disables(state, old_crtc_state, new_crtc_state, crtc); } @@ -6922,8 +7023,10 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) continue; if (intel_dp_mst_is_slave_trans(new_crtc_state) || - is_trans_port_sync_master(new_crtc_state) || - intel_crtc_is_bigjoiner_master(new_crtc_state)) + is_trans_port_sync_master(new_crtc_state)) + continue; + + if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) continue; modeset_pipes &= ~BIT(pipe); @@ -6933,7 +7036,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) /* * Then we enable all remaining pipes that depend on other - * pipes: MST slaves and port sync masters, big joiner master + * pipes: MST slaves and port sync masters */ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { enum pipe pipe = crtc->pipe; @@ -6941,6 +7044,9 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((modeset_pipes & BIT(pipe)) == 0) continue; + if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) + continue; + modeset_pipes &= ~BIT(pipe); intel_enable_crtc(state, crtc);
Handle only bigjoiner masters in skl_commit_modeset_enables/disables, slave crtcs should be handled by master hooks. Same for encoders. That way we can also remove a bunch of checks like intel_crtc_is_bigjoiner_slave. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 +- drivers/gpu/drm/i915/display/intel_display.c | 148 ++++++++++++++++--- 2 files changed, 128 insertions(+), 23 deletions(-)