| Message ID | 20231113185607.1756-3-james.quinlan@broadcom.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCI: brcmstb: Configure appropriate HW CLKREQ# mode | expand |
On 11/13/23 10:56, Jim Quinlan wrote: > The Broadcom STB/CM PCIe HW core, which is also used in RPi SOCs, must be > deliberately set by the PCIe RC HW into one of three mutually exclusive > modes: > > "safe" -- No CLKREQ# expected or required, refclk is always provided. This > mode should work for all devices but is not be capable of any refclk > power savings. > > "no-l1ss" -- CLKREQ# is expected to be driven by the downstream device for > CPM and ASPM L0s and L1. Provides Clock Power Management, L0s, and L1, > but cannot provide L1 substate (L1SS) power savings. If the downstream > device connected to the RC is L1SS capable AND the OS enables L1SS, all > PCIe traffic may abruptly halt, potentially hanging the system. > > "default" -- Bidirectional CLKREQ# between the RC and downstream device. > Provides ASPM L0s, L1, and L1SS, but not compliant to provide Clock > Power Management; specifically, may not be able to meet the T_CLRon max > timing of 400ns as specified in "Dynamic Clock Control", section > 3.2.5.2.2 of the PCIe Express Mini CEM 2.1 specification. This > situation is atypical and should happen only with older devices. > > Previously, this driver always set the mode to "no-l1ss", as almost all > STB/CM boards operate in this mode. But now there is interest in > activating L1SS power savings from STB/CM customers, which requires "aspm" > mode. In addition, a bug was filed for RPi4 CM platform because most > devices did not work in "no-l1ss" mode. > > Note that the mode is specified by the DT property "brcm,clkreq-mode". If > this property is omitted, then "default" mode is chosen. > > Note: Since L1 substates are now possible, a modification was made > regarding an internal bus timeout: During long periods of the PCIe RC HW > being in an L1SS sleep state, there may be a timeout on an internal bus > access, even though there may not be any PCIe access involved. Such a > timeout will cause a subsequent CPU abort. > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=217276 > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> > Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> I don't think you could have carried that Tested-by tag given that I tested the previous version which is subtly different from this one, but since I now just did test this v8 and all is still well, I suppose that works just as well. Thanks!
On Mon, Nov 13, 2023 at 01:56:06PM -0500, Jim Quinlan wrote: > The Broadcom STB/CM PCIe HW core, which is also used in RPi SOCs, must be > deliberately set by the PCIe RC HW into one of three mutually exclusive > modes: > > "safe" -- No CLKREQ# expected or required, refclk is always provided. This > mode should work for all devices but is not be capable of any refclk > power savings. > > "no-l1ss" -- CLKREQ# is expected to be driven by the downstream device for > CPM and ASPM L0s and L1. Provides Clock Power Management, L0s, and L1, > but cannot provide L1 substate (L1SS) power savings. If the downstream > device connected to the RC is L1SS capable AND the OS enables L1SS, all > PCIe traffic may abruptly halt, potentially hanging the system. > > "default" -- Bidirectional CLKREQ# between the RC and downstream device. > Provides ASPM L0s, L1, and L1SS, but not compliant to provide Clock > Power Management; specifically, may not be able to meet the T_CLRon max > timing of 400ns as specified in "Dynamic Clock Control", section > 3.2.5.2.2 of the PCIe Express Mini CEM 2.1 specification. This > situation is atypical and should happen only with older devices. > > Previously, this driver always set the mode to "no-l1ss", as almost all > STB/CM boards operate in this mode. But now there is interest in > activating L1SS power savings from STB/CM customers, which requires "aspm" > mode. I think this should read "default" mode, not "aspm" mode, since "aspm" is not a mode implemented by this patch, right? > In addition, a bug was filed for RPi4 CM platform because most > devices did not work in "no-l1ss" mode. I think this refers to bug 217276, mentioned below? > Note that the mode is specified by the DT property "brcm,clkreq-mode". If > this property is omitted, then "default" mode is chosen. > > Note: Since L1 substates are now possible, a modification was made > regarding an internal bus timeout: During long periods of the PCIe RC HW > being in an L1SS sleep state, there may be a timeout on an internal bus > access, even though there may not be any PCIe access involved. Such a > timeout will cause a subsequent CPU abort. This sounds scary. If a NIC is put in L1.2, does this mean will we see this CPU abort if there's no traffic for a long time? What is needed to avoid the CPU abort? What does this mean for users? L1SS is designed for long periods of the device being idle, so this leaves me feeling that using L1SS is unsafe in general. Hopefully this impression is unwarranted, and all we need is some clarification here. > Link: https://bugzilla.kernel.org/show_bug.cgi?id=217276 > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> > Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> > --- > drivers/pci/controller/pcie-brcmstb.c | 96 ++++++++++++++++++++++++--- > 1 file changed, 86 insertions(+), 10 deletions(-) > ...
On Thu, Jan 11, 2024 at 12:28 PM Bjorn Helgaas <helgaas@kernel.org> wrote: > > On Mon, Nov 13, 2023 at 01:56:06PM -0500, Jim Quinlan wrote: > > The Broadcom STB/CM PCIe HW core, which is also used in RPi SOCs, must be > > deliberately set by the PCIe RC HW into one of three mutually exclusive > > modes: > > > > "safe" -- No CLKREQ# expected or required, refclk is always provided. This > > mode should work for all devices but is not be capable of any refclk > > power savings. > > > > "no-l1ss" -- CLKREQ# is expected to be driven by the downstream device for > > CPM and ASPM L0s and L1. Provides Clock Power Management, L0s, and L1, > > but cannot provide L1 substate (L1SS) power savings. If the downstream > > device connected to the RC is L1SS capable AND the OS enables L1SS, all > > PCIe traffic may abruptly halt, potentially hanging the system. > > > > "default" -- Bidirectional CLKREQ# between the RC and downstream device. > > Provides ASPM L0s, L1, and L1SS, but not compliant to provide Clock > > Power Management; specifically, may not be able to meet the T_CLRon max > > timing of 400ns as specified in "Dynamic Clock Control", section > > 3.2.5.2.2 of the PCIe Express Mini CEM 2.1 specification. This > > situation is atypical and should happen only with older devices. > > > > Previously, this driver always set the mode to "no-l1ss", as almost all > > STB/CM boards operate in this mode. But now there is interest in > > activating L1SS power savings from STB/CM customers, which requires "aspm" > > mode. > > I think this should read "default" mode, not "aspm" mode, since "aspm" > is not a mode implemented by this patch, right? Correct. > > > > In addition, a bug was filed for RPi4 CM platform because most > > devices did not work in "no-l1ss" mode. > > I think this refers to bug 217276, mentioned below? I guess you are saying I should put a footnote marker there. > > > > Note that the mode is specified by the DT property "brcm,clkreq-mode". If > > this property is omitted, then "default" mode is chosen. > > > > Note: Since L1 substates are now possible, a modification was made > > regarding an internal bus timeout: During long periods of the PCIe RC HW > > being in an L1SS sleep state, there may be a timeout on an internal bus > > access, even though there may not be any PCIe access involved. Such a > > timeout will cause a subsequent CPU abort. > > This sounds scary. If a NIC is put in L1.2, does this mean will we > see this CPU abort if there's no traffic for a long time? What is > needed to avoid the CPU abort? I don't think this happens in normal practice as there are a slew of low-level TLPs and LTR messages that are sent on a regular basis. The only time this timeout occured is when a major customer was doing a hack: IIRC, their endpoint device has to reboot itself after link-up and driver probe, so it goes into L1.2 to execute this to reboot and while doing so the connection is completely silent. > > Rega > What does this mean for users? L1SS is designed for long periods of > the device being idle, so this leaves me feeling that using L1SS is > unsafe in general. Hopefully this impression is unwarranted, and all > we need is some clarification here. I don't think it will affect most users, if any. Regards, Jim Quinlan Broadcom STB/CM > > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=217276 > > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> > > Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> > > --- > > drivers/pci/controller/pcie-brcmstb.c | 96 ++++++++++++++++++++++++--- > > 1 file changed, 86 insertions(+), 10 deletions(-) > > ...
On Thu, Jan 11, 2024 at 01:20:48PM -0500, Jim Quinlan wrote: > On Thu, Jan 11, 2024 at 12:28 PM Bjorn Helgaas <helgaas@kernel.org> wrote: > > On Mon, Nov 13, 2023 at 01:56:06PM -0500, Jim Quinlan wrote: > > > Previously, this driver always set the mode to "no-l1ss", as almost all > > > STB/CM boards operate in this mode. But now there is interest in > > > activating L1SS power savings from STB/CM customers, which requires "aspm" > > > mode. > > > > I think this should read "default" mode, not "aspm" mode, since "aspm" > > is not a mode implemented by this patch, right? > > Correct. Thanks, I changed that locally. > > > In addition, a bug was filed for RPi4 CM platform because most > > > devices did not work in "no-l1ss" mode. > > > > I think this refers to bug 217276, mentioned below? > > I guess you are saying I should put a footnote marker there. I added a hint here. > > > Note: Since L1 substates are now possible, a modification was made > > > regarding an internal bus timeout: During long periods of the PCIe RC HW > > > being in an L1SS sleep state, there may be a timeout on an internal bus > > > access, even though there may not be any PCIe access involved. Such a > > > timeout will cause a subsequent CPU abort. > > > > This sounds scary. If a NIC is put in L1.2, does this mean will we > > see this CPU abort if there's no traffic for a long time? What is > > needed to avoid the CPU abort? > > I don't think this happens in normal practice as there are a slew > of low-level TLPs and LTR messages that are sent on a regular > basis. OK, I'll have to take your word for this. I don't know enough about PCIe to know what sort of periodic transmissions are required when a device is idle. LTR messages are required when endpoint service requirements change, but I wouldn't expect those if the device is idle. > The only time this timeout occured is when a major customer > was doing a hack: IIRC, their endpoint device has to reboot itself > after link-up and driver probe, so it goes into L1.2 to execute > this to reboot and while doing so the connection is completely > silent. > > What does this mean for users? L1SS is designed for long periods of > > the device being idle, so this leaves me feeling that using L1SS is > > unsafe in general. Hopefully this impression is unwarranted, and all > > we need is some clarification here. > > I don't think it will affect most users, if any. I'll try to get this into -next today or tomorrow. Bjorn
On Thu, Jan 11, 2024 at 3:54 PM Bjorn Helgaas <helgaas@kernel.org> wrote: > > On Thu, Jan 11, 2024 at 01:20:48PM -0500, Jim Quinlan wrote: > > On Thu, Jan 11, 2024 at 12:28 PM Bjorn Helgaas <helgaas@kernel.org> wrote: > > > On Mon, Nov 13, 2023 at 01:56:06PM -0500, Jim Quinlan wrote: > > > > > Previously, this driver always set the mode to "no-l1ss", as almost all > > > > STB/CM boards operate in this mode. But now there is interest in > > > > activating L1SS power savings from STB/CM customers, which requires "aspm" > > > > mode. > > > > > > I think this should read "default" mode, not "aspm" mode, since "aspm" > > > is not a mode implemented by this patch, right? > > > > Correct. > > Thanks, I changed that locally. > > > > > In addition, a bug was filed for RPi4 CM platform because most > > > > devices did not work in "no-l1ss" mode. > > > > > > I think this refers to bug 217276, mentioned below? > > > > I guess you are saying I should put a footnote marker there. > > I added a hint here. > > > > > Note: Since L1 substates are now possible, a modification was made > > > > regarding an internal bus timeout: During long periods of the PCIe RC HW > > > > being in an L1SS sleep state, there may be a timeout on an internal bus > > > > access, even though there may not be any PCIe access involved. Such a > > > > timeout will cause a subsequent CPU abort. > > > > > > This sounds scary. If a NIC is put in L1.2, does this mean will we > > > see this CPU abort if there's no traffic for a long time? What is > > > needed to avoid the CPU abort? > > > > I don't think this happens in normal practice as there are a slew > > of low-level TLPs and LTR messages that are sent on a regular > > basis. > > OK, I'll have to take your word for this. I don't know enough about > PCIe to know what sort of periodic transmissions are required when a > device is idle. > > LTR messages are required when endpoint service requirements change, > but I wouldn't expect those if the device is idle. > > > The only time this timeout occured is when a major customer > > was doing a hack: IIRC, their endpoint device has to reboot itself > > after link-up and driver probe, so it goes into L1.2 to execute > > this to reboot and while doing so the connection is completely > > silent. > > > > What does this mean for users? L1SS is designed for long periods of > > > the device being idle, so this leaves me feeling that using L1SS is > > > unsafe in general. Hopefully this impression is unwarranted, and all > > > we need is some clarification here. > > > > I don't think it will affect most users, if any. > > I'll try to get this into -next today or tomorrow. Bjorn, you are right -- I need to cajole our PCIe HW team to tell me why this timeout can never happen and/or why it is not a bug. Until then, Jim Quinlan Broadcom STB/CM If > > Bjorn
On Sun, Jan 14, 2024 at 05:03:43PM -0500, Jim Quinlan wrote: > On Thu, Jan 11, 2024 at 3:54 PM Bjorn Helgaas <helgaas@kernel.org> wrote: > > On Thu, Jan 11, 2024 at 01:20:48PM -0500, Jim Quinlan wrote: > > > On Thu, Jan 11, 2024 at 12:28 PM Bjorn Helgaas <helgaas@kernel.org> wrote: > > > > On Mon, Nov 13, 2023 at 01:56:06PM -0500, Jim Quinlan wrote: > ... > > > > > Note: Since L1 substates are now possible, a modification was made > > > > > regarding an internal bus timeout: During long periods of the PCIe RC HW > > > > > being in an L1SS sleep state, there may be a timeout on an internal bus > > > > > access, even though there may not be any PCIe access involved. Such a > > > > > timeout will cause a subsequent CPU abort. > > > > > > > > This sounds scary. If a NIC is put in L1.2, does this mean will we > > > > see this CPU abort if there's no traffic for a long time? What is > > > > needed to avoid the CPU abort? > > > > > > I don't think this happens in normal practice as there are a slew > > > of low-level TLPs and LTR messages that are sent on a regular > > > basis. > > > > OK, I'll have to take your word for this. I don't know enough about > > PCIe to know what sort of periodic transmissions are required when a > > device is idle. > > > > LTR messages are required when endpoint service requirements change, > > but I wouldn't expect those if the device is idle. > > > > > The only time this timeout occured is when a major customer > > > was doing a hack: IIRC, their endpoint device has to reboot itself > > > after link-up and driver probe, so it goes into L1.2 to execute > > > this to reboot and while doing so the connection is completely > > > silent. > > > > > > What does this mean for users? L1SS is designed for long periods of > > > > the device being idle, so this leaves me feeling that using L1SS is > > > > unsafe in general. Hopefully this impression is unwarranted, and all > > > > we need is some clarification here. > > > > > > I don't think it will affect most users, if any. > > > > I'll try to get this into -next today or tomorrow. > > Bjorn, you are right -- I need to cajole our PCIe HW team to tell me > why this timeout can never > happen and/or why it is not a bug. It'll be good to hear what they have to say. I will include this patch in my pull request for v6.8 unless you want me to wait on it. I hope to send the pull request tomorrow or Tuesday at the latest. Bjorn
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index f9dd6622fe10..5b0730c3891b 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -48,6 +48,9 @@ #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00 +#define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f8 +#define PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK 0xf8 + #define PCIE_RC_DL_MDIO_ADDR 0x1100 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 @@ -121,9 +124,12 @@ #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000 - +#define PCIE_CLKREQ_MASK \ + (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \ + PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK) #define PCIE_INTR2_CPU_BASE 0x4300 #define PCIE_MSI_INTR2_BASE 0x4500 @@ -1028,13 +1034,89 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return 0; } +/* + * This extends the timeout period for an access to an internal bus. This + * access timeout may occur during L1SS sleep periods, even without the + * presence of a PCIe access. + */ +static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) +{ + /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */ + const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; + u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */ + + /* Each unit in timeout register is 1/216,000,000 seconds */ + writel(216 * timeout_us, pcie->base + REG_OFFSET); +} + +static void brcm_config_clkreq(struct brcm_pcie *pcie) +{ + static const char err_msg[] = "invalid 'brcm,clkreq-mode' DT string\n"; + const char *mode = "default"; + u32 clkreq_cntl; + int ret, tmp; + + ret = of_property_read_string(pcie->np, "brcm,clkreq-mode", &mode); + if (ret && ret != -EINVAL) { + dev_err(pcie->dev, err_msg); + mode = "safe"; + } + + /* Start out assuming safe mode (both mode bits cleared) */ + clkreq_cntl = readl(pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + clkreq_cntl &= ~PCIE_CLKREQ_MASK; + + if (strcmp(mode, "no-l1ss") == 0) { + /* + * "no-l1ss" -- Provides Clock Power Management, L0s, and + * L1, but cannot provide L1 substate (L1SS) power + * savings. If the downstream device connected to the RC is + * L1SS capable AND the OS enables L1SS, all PCIe traffic + * may abruptly halt, potentially hanging the system. + */ + clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; + /* + * We want to un-advertise L1 substates because if the OS + * tries to configure the controller into using L1 substate + * power savings it may fail or hang when the RC HW is in + * "no-l1ss" mode. + */ + tmp = readl(pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); + u32p_replace_bits(&tmp, 2, PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK); + writel(tmp, pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); + + } else if (strcmp(mode, "default") == 0) { + /* + * "default" -- Provides L0s, L1, and L1SS, but not + * compliant to provide Clock Power Management; + * specifically, may not be able to meet the Tclron max + * timing of 400ns as specified in "Dynamic Clock Control", + * section 3.2.5.2.2 of the PCIe spec. This situation is + * atypical and should happen only with older devices. + */ + clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK; + brcm_extend_rbus_timeout(pcie); + + } else { + /* + * "safe" -- No power savings; refclk is driven by RC + * unconditionally. + */ + if (strcmp(mode, "safe") != 0) + dev_err(pcie->dev, err_msg); + mode = "safe"; + } + writel(clkreq_cntl, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + + dev_info(pcie->dev, "clkreq-mode set to %s\n", mode); +} + static int brcm_pcie_start_link(struct brcm_pcie *pcie) { struct device *dev = pcie->dev; void __iomem *base = pcie->base; u16 nlw, cls, lnksta; bool ssc_good = false; - u32 tmp; int ret, i; /* Unassert the fundamental reset */ @@ -1059,6 +1141,8 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) return -ENODEV; } + brcm_config_clkreq(pcie); + if (pcie->gen) brcm_pcie_set_gen(pcie, pcie->gen); @@ -1077,14 +1161,6 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) pci_speed_string(pcie_link_speed[cls]), nlw, ssc_good ? "(SSC)" : "(!SSC)"); - /* - * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 - * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. - */ - tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); - tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); - return 0; }
The Broadcom STB/CM PCIe HW core, which is also used in RPi SOCs, must be deliberately set by the PCIe RC HW into one of three mutually exclusive modes: "safe" -- No CLKREQ# expected or required, refclk is always provided. This mode should work for all devices but is not be capable of any refclk power savings. "no-l1ss" -- CLKREQ# is expected to be driven by the downstream device for CPM and ASPM L0s and L1. Provides Clock Power Management, L0s, and L1, but cannot provide L1 substate (L1SS) power savings. If the downstream device connected to the RC is L1SS capable AND the OS enables L1SS, all PCIe traffic may abruptly halt, potentially hanging the system. "default" -- Bidirectional CLKREQ# between the RC and downstream device. Provides ASPM L0s, L1, and L1SS, but not compliant to provide Clock Power Management; specifically, may not be able to meet the T_CLRon max timing of 400ns as specified in "Dynamic Clock Control", section 3.2.5.2.2 of the PCIe Express Mini CEM 2.1 specification. This situation is atypical and should happen only with older devices. Previously, this driver always set the mode to "no-l1ss", as almost all STB/CM boards operate in this mode. But now there is interest in activating L1SS power savings from STB/CM customers, which requires "aspm" mode. In addition, a bug was filed for RPi4 CM platform because most devices did not work in "no-l1ss" mode. Note that the mode is specified by the DT property "brcm,clkreq-mode". If this property is omitted, then "default" mode is chosen. Note: Since L1 substates are now possible, a modification was made regarding an internal bus timeout: During long periods of the PCIe RC HW being in an L1SS sleep state, there may be a timeout on an internal bus access, even though there may not be any PCIe access involved. Such a timeout will cause a subsequent CPU abort. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217276 Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> --- drivers/pci/controller/pcie-brcmstb.c | 96 ++++++++++++++++++++++++--- 1 file changed, 86 insertions(+), 10 deletions(-)