| Message ID | e6d7768e2a257e0bd5948bcf168909b6c670851b.1705168605.git.lukas@wunner.de (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 5e2400f11d4deec444ac00b73e96267e057fbb37 |
| Headers | show |
| Series | arm64: dts: Fix TPM schema violations | expand |
Hi Lukas, Am Samstag, 13. Januar 2024, 19:06:56 CET schrieb Lukas Wunner: > Since commit 26c9d152ebf3 ("dt-bindings: tpm: Consolidate TCG TIS > bindings"), several issues are reported by "make dtbs_check" for arm64 > devicetrees: > > The compatible property needs to contain the chip's name in addition to > the generic "tcg,tpm_tis-spi" and the nodename needs to be "tpm@0" > rather than "cr50@0": > > tpm@1: compatible: ['tcg,tpm_tis-spi'] is too short > from schema $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml# > > cr50@0: $nodename:0: 'cr50@0' does not match '^tpm(@[0-9a-f]+)?$' > from schema $id: http://devicetree.org/schemas/tpm/google,cr50.yaml# > > Fix these schema violations. > > phyGATE-Tauri uses an Infineon SLB9670: > https://lore.kernel.org/all/ab45c82485fa272f74adf560cbb58ee60cc42689.camel@phytec.de/ > > Gateworks Venice uses an Atmel ATTPM20P: > https://trac.gateworks.com/wiki/tpm > > Signed-off-by: Lukas Wunner <lukas@wunner.de> > --- > The commit mentioned above, 26c9d152ebf3 ("dt-bindings: tpm: Consolidate > TCG TIS bindings") landed in Linus' tree yesterday. > > Because this consists only of fixes, I think it could be picked up and > forwarded to Linus at any time, even outside the merge window. > > The issues reported for imx8m*-venice-gw7*xx.dts* devicetrees will not > go away until Jarrko picks up this amendment patch for the dt-bindings: > https://lore.kernel.org/all/8886271d52025065eddf5915bb7778ab14362255.1705140898.git.lukas@wunner.de/ > > arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts | 2 +- > arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 2 +- > arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 2 +- > arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts | 2 +- > arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi | 2 +- > arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi | 2 +- > arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 2 +- > arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts | 2 +- > arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 +- > arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 2 +- > arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts | 2 +- > arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 2 +- you might want to split this per sub-architecture perhaps (freescale, mediatek, rockchip) as such dts changes normally go through the trees of the subarchitecture maintainers. For the rockchip-parts itself, I'm also fine with them going through somewhere else - gru devices are pretty much "finished" by now, so for the rockchip changes Acked-by: Heiko Stuebner <heiko@sntech.de> Heiko
On Sat, Jan 13, 2024 at 08:13:35PM +0100, Heiko Stübner wrote: > Am Samstag, 13. Januar 2024, 19:06:56 CET schrieb Lukas Wunner: > > Since commit 26c9d152ebf3 ("dt-bindings: tpm: Consolidate TCG TIS > > bindings"), several issues are reported by "make dtbs_check" for arm64 > > devicetrees: > > > > The compatible property needs to contain the chip's name in addition to > > the generic "tcg,tpm_tis-spi" and the nodename needs to be "tpm@0" > > rather than "cr50@0": > > > > tpm@1: compatible: ['tcg,tpm_tis-spi'] is too short > > from schema $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml# > > > > cr50@0: $nodename:0: 'cr50@0' does not match '^tpm(@[0-9a-f]+)?$' > > from schema $id: http://devicetree.org/schemas/tpm/google,cr50.yaml# > > > > Fix these schema violations. [...] > > arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts | 2 +- > > arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 2 +- > > arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 2 +- > > arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts | 2 +- > > arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi | 2 +- > > arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi | 2 +- > > arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 2 +- > > arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts | 2 +- > > arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 +- > > arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 2 +- > > arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts | 2 +- > > arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 2 +- > > you might want to split this per sub-architecture perhaps (freescale, > mediatek, rockchip) as such dts changes normally go through the trees > of the subarchitecture maintainers. My concern was that other developers may see these new warnings and start submitting piecemeal fixes. That would be a waste of time since I already prepared fixes for everything weeks ago. I was only waiting for the schema changes to hit mainline. I was hoping that these might make it to Linus during the back half of the merge window so that the warnings are gone by rc1 time and nobody will ever see them. Of course I can split them up if that's what Arnd & Olof prefer. > For the rockchip-parts itself, I'm also fine with them going through > somewhere else - gru devices are pretty much "finished" by now, > so for the rockchip changes > Acked-by: Heiko Stuebner <heiko@sntech.de> Thanks for taking a look! Lukas
Il 13/01/24 19:06, Lukas Wunner ha scritto: > Since commit 26c9d152ebf3 ("dt-bindings: tpm: Consolidate TCG TIS > bindings"), several issues are reported by "make dtbs_check" for arm64 > devicetrees: > > The compatible property needs to contain the chip's name in addition to > the generic "tcg,tpm_tis-spi" and the nodename needs to be "tpm@0" > rather than "cr50@0": > > tpm@1: compatible: ['tcg,tpm_tis-spi'] is too short > from schema $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml# > > cr50@0: $nodename:0: 'cr50@0' does not match '^tpm(@[0-9a-f]+)?$' > from schema $id: http://devicetree.org/schemas/tpm/google,cr50.yaml# > > Fix these schema violations. > > phyGATE-Tauri uses an Infineon SLB9670: > https://lore.kernel.org/all/ab45c82485fa272f74adf560cbb58ee60cc42689.camel@phytec.de/ > > Gateworks Venice uses an Atmel ATTPM20P: > https://trac.gateworks.com/wiki/tpm > > Signed-off-by: Lukas Wunner <lukas@wunner.de> For MediaTek: Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> ...but I think you should split this per-SoC. Anyway, if Arnd wants to take this patch directly I'm also totally fine with that. Cheers, Angelo
On Mon, Jan 15, 2024, at 09:41, AngeloGioacchino Del Regno wrote: > Il 13/01/24 19:06, Lukas Wunner ha scritto: >> Since commit 26c9d152ebf3 ("dt-bindings: tpm: Consolidate TCG TIS >> bindings"), several issues are reported by "make dtbs_check" for arm64 >> devicetrees: >> >> The compatible property needs to contain the chip's name in addition to >> the generic "tcg,tpm_tis-spi" and the nodename needs to be "tpm@0" >> rather than "cr50@0": >> >> tpm@1: compatible: ['tcg,tpm_tis-spi'] is too short >> from schema $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml# >> >> cr50@0: $nodename:0: 'cr50@0' does not match '^tpm(@[0-9a-f]+)?$' >> from schema $id: http://devicetree.org/schemas/tpm/google,cr50.yaml# >> >> Fix these schema violations. >> >> phyGATE-Tauri uses an Infineon SLB9670: >> https://lore.kernel.org/all/ab45c82485fa272f74adf560cbb58ee60cc42689.camel@phytec.de/ >> >> Gateworks Venice uses an Atmel ATTPM20P: >> https://trac.gateworks.com/wiki/tpm >> >> Signed-off-by: Lukas Wunner <lukas@wunner.de> > > For MediaTek: > Reviewed-by: AngeloGioacchino Del Regno > <angelogioacchino.delregno@collabora.com> > > ...but I think you should split this per-SoC. > > Anyway, if Arnd wants to take this patch directly I'm also totally fine > with that. I would prefer to apply the combined patches: if you end up with a series of patches that all have identical commit texts, it's better to combine them as that gives a more readable git history. However, I got some conflicts trying to apply them on top of v6.7, so maybe check that and resend. Arnd
On Mon, Jan 15, 2024 at 09:17:41PM +0100, Arnd Bergmann wrote: > > Il 13/01/24 19:06, Lukas Wunner ha scritto: > > > Since commit 26c9d152ebf3 ("dt-bindings: tpm: Consolidate TCG TIS > > > bindings"), several issues are reported by "make dtbs_check" for arm64 > > > devicetrees: > > > > > > The compatible property needs to contain the chip's name in addition to > > > the generic "tcg,tpm_tis-spi" and the nodename needs to be "tpm@0" > > > rather than "cr50@0": > > > > > > tpm@1: compatible: ['tcg,tpm_tis-spi'] is too short > > > from schema $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml# > > > > > > cr50@0: $nodename:0: 'cr50@0' does not match '^tpm(@[0-9a-f]+)?$' > > > from schema $id: http://devicetree.org/schemas/tpm/google,cr50.yaml# > > > > > > Fix these schema violations. > > However, I got some conflicts trying to apply them on > top of v6.7, so maybe check that and resend. This patch needs to be applied on top of the soc-dt-6.8 tag, not v6.7, because there were changes in your v6.8 pull request which introduce a new TPM DT node in: arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi and modify an existing TPM DT node in: arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts So if I'd base this patch on top of v6.7, it would be missing the fixes for these three devicetrees and I'd have to submit a separate patch with them. Happy to do so if that's what you want but basing on top of soc-dt-6.8 seemed more reasonable to me as initial submission. Thanks! Lukas
Hello: This patch was applied to soc/soc.git (arm/fixes) by Arnd Bergmann <arnd@arndb.de>: On Sat, 13 Jan 2024 19:06:56 +0100 you wrote: > Since commit 26c9d152ebf3 ("dt-bindings: tpm: Consolidate TCG TIS > bindings"), several issues are reported by "make dtbs_check" for arm64 > devicetrees: > > The compatible property needs to contain the chip's name in addition to > the generic "tcg,tpm_tis-spi" and the nodename needs to be "tpm@0" > rather than "cr50@0": > > [...] Here is the summary with links: - arm64: dts: Fix TPM schema violations https://git.kernel.org/soc/soc/c/5e2400f11d4d You are awesome, thank you!
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts index 968f475..27a9025 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts @@ -120,7 +120,7 @@ }; tpm: tpm@1 { - compatible = "tcg,tpm_tis-spi"; + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio2>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index 3f3f2a2..752caa3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -89,7 +89,7 @@ status = "okay"; tpm@1 { - compatible = "tcg,tpm_tis-spi"; + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; reg = <0x1>; spi-max-frequency = <36000000>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index 06fed93..2aa6c10 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -109,7 +109,7 @@ status = "okay"; tpm@1 { - compatible = "tcg,tpm_tis-spi"; + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; reg = <0x1>; spi-max-frequency = <36000000>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index feae77e..a080574 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -234,7 +234,7 @@ status = "okay"; tpm: tpm@0 { - compatible = "infineon,slb9670"; + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tpm>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi index c24587c..41c79d2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi @@ -103,7 +103,7 @@ status = "okay"; tpm@1 { - compatible = "tcg,tpm_tis-spi"; + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; reg = <0x1>; spi-max-frequency = <36000000>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi index 628ffba6..d5c400b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi @@ -115,7 +115,7 @@ status = "okay"; tpm@1 { - compatible = "tcg,tpm_tis-spi"; + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; reg = <0x1>; spi-max-frequency = <36000000>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index 9caf7ca..cae586c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -196,7 +196,7 @@ status = "okay"; tpm@0 { - compatible = "tcg,tpm_tis-spi"; + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; reg = <0x0>; spi-max-frequency = <36000000>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts index 6376417..d8cf1f2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts @@ -65,7 +65,7 @@ status = "okay"; tpm@0 { - compatible = "infineon,slb9670"; + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <43000000>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 5506de8..1b3396b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -888,7 +888,7 @@ status = "okay"; cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>; - cr50@0 { + tpm@0 { compatible = "google,cr50"; reg = <0>; spi-max-frequency = <1000000>; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index f228125..d87aab8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -1402,7 +1402,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi5_pins>; - cr50@0 { + tpm@0 { compatible = "google,cr50"; reg = <0>; interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts index 0f9cc04..1cba1d8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts @@ -70,7 +70,7 @@ &spi0 { status = "okay"; - cr50@0 { + tpm@0 { compatible = "google,cr50"; reg = <0>; interrupt-parent = <&gpio0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index c5e7de6..5846a11 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -706,7 +706,7 @@ camera: &i2c7 { &spi2 { status = "okay"; - cr50@0 { + tpm@0 { compatible = "google,cr50"; reg = <0>; interrupt-parent = <&gpio1>;
Since commit 26c9d152ebf3 ("dt-bindings: tpm: Consolidate TCG TIS bindings"), several issues are reported by "make dtbs_check" for arm64 devicetrees: The compatible property needs to contain the chip's name in addition to the generic "tcg,tpm_tis-spi" and the nodename needs to be "tpm@0" rather than "cr50@0": tpm@1: compatible: ['tcg,tpm_tis-spi'] is too short from schema $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml# cr50@0: $nodename:0: 'cr50@0' does not match '^tpm(@[0-9a-f]+)?$' from schema $id: http://devicetree.org/schemas/tpm/google,cr50.yaml# Fix these schema violations. phyGATE-Tauri uses an Infineon SLB9670: https://lore.kernel.org/all/ab45c82485fa272f74adf560cbb58ee60cc42689.camel@phytec.de/ Gateworks Venice uses an Atmel ATTPM20P: https://trac.gateworks.com/wiki/tpm Signed-off-by: Lukas Wunner <lukas@wunner.de> --- The commit mentioned above, 26c9d152ebf3 ("dt-bindings: tpm: Consolidate TCG TIS bindings") landed in Linus' tree yesterday. Because this consists only of fixes, I think it could be picked up and forwarded to Linus at any time, even outside the merge window. The issues reported for imx8m*-venice-gw7*xx.dts* devicetrees will not go away until Jarrko picks up this amendment patch for the dt-bindings: https://lore.kernel.org/all/8886271d52025065eddf5915bb7778ab14362255.1705140898.git.lukas@wunner.de/ arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts | 2 +- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-)