diff mbox series

[v5,2/2] riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint format

Message ID IA1PR20MB4953669C097D9C9E24B549FFBB86A@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive)
State Superseded
Delegated to: Conor Dooley
Headers show
Series Change the sg2042 timer layout to fit aclint format | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-2-test-1 success .github/scripts/patches/build_rv32_defconfig.sh
conchuod/patch-2-test-2 success .github/scripts/patches/build_rv64_clang_allmodconfig.sh
conchuod/patch-2-test-3 success .github/scripts/patches/build_rv64_gcc_allmodconfig.sh
conchuod/patch-2-test-4 success .github/scripts/patches/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-2-test-5 success .github/scripts/patches/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-2-test-6 success .github/scripts/patches/checkpatch.sh
conchuod/patch-2-test-7 success .github/scripts/patches/dtb_warn_rv64.sh
conchuod/patch-2-test-8 success .github/scripts/patches/header_inline.sh
conchuod/patch-2-test-9 success .github/scripts/patches/kdoc.sh
conchuod/patch-2-test-10 success .github/scripts/patches/module_param.sh
conchuod/patch-2-test-11 success .github/scripts/patches/verify_fixes.sh
conchuod/patch-2-test-12 success .github/scripts/patches/verify_signedoff.sh

Commit Message

Inochi Amaoto Dec. 4, 2023, 9:51 a.m. UTC 
Change the timer layout in the dtb to fit the format that needed by
the SBI.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree")
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
---
 arch/riscv/boot/dts/sophgo/sg2042.dtsi | 80 +++++++++++++++-----------
 1 file changed, 48 insertions(+), 32 deletions(-)

--
2.43.0

Comments

Guo Ren Dec. 4, 2023, 2:51 p.m. UTC | #1 
On Mon, Dec 4, 2023 at 5:51 PM Inochi Amaoto <inochiama@outlook.com> wrote:
>
> Change the timer layout in the dtb to fit the format that needed by
> the SBI.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree")
> Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi | 80 +++++++++++++++-----------
>  1 file changed, 48 insertions(+), 32 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index 93256540d078..ead1cc35d88b 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -93,144 +93,160 @@ clint_mswi: interrupt-controller@7094000000 {
>                                               <&cpu63_intc 3>;
>                 };
>
> -               clint_mtimer0: timer@70ac000000 {
> +               clint_mtimer0: timer@70ac004000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu0_intc 7>,
>                                               <&cpu1_intc 7>,
>                                               <&cpu2_intc 7>,
>                                               <&cpu3_intc 7>;
>                 };
>
> -               clint_mtimer1: timer@70ac010000 {
> +               clint_mtimer1: timer@70ac014000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu4_intc 7>,
>                                               <&cpu5_intc 7>,
>                                               <&cpu6_intc 7>,
>                                               <&cpu7_intc 7>;
>                 };
>
> -               clint_mtimer2: timer@70ac020000 {
> +               clint_mtimer2: timer@70ac024000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu8_intc 7>,
>                                               <&cpu9_intc 7>,
>                                               <&cpu10_intc 7>,
>                                               <&cpu11_intc 7>;
>                 };
>
> -               clint_mtimer3: timer@70ac030000 {
> +               clint_mtimer3: timer@70ac034000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu12_intc 7>,
>                                               <&cpu13_intc 7>,
>                                               <&cpu14_intc 7>,
>                                               <&cpu15_intc 7>;
>                 };
>
> -               clint_mtimer4: timer@70ac040000 {
> +               clint_mtimer4: timer@70ac044000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu16_intc 7>,
>                                               <&cpu17_intc 7>,
>                                               <&cpu18_intc 7>,
>                                               <&cpu19_intc 7>;
>                 };
>
> -               clint_mtimer5: timer@70ac050000 {
> +               clint_mtimer5: timer@70ac054000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu20_intc 7>,
>                                               <&cpu21_intc 7>,
>                                               <&cpu22_intc 7>,
>                                               <&cpu23_intc 7>;
>                 };
>
> -               clint_mtimer6: timer@70ac060000 {
> +               clint_mtimer6: timer@70ac064000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu24_intc 7>,
>                                               <&cpu25_intc 7>,
>                                               <&cpu26_intc 7>,
>                                               <&cpu27_intc 7>;
>                 };
>
> -               clint_mtimer7: timer@70ac070000 {
> +               clint_mtimer7: timer@70ac074000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu28_intc 7>,
>                                               <&cpu29_intc 7>,
>                                               <&cpu30_intc 7>,
>                                               <&cpu31_intc 7>;
>                 };
>
> -               clint_mtimer8: timer@70ac080000 {
> +               clint_mtimer8: timer@70ac084000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu32_intc 7>,
>                                               <&cpu33_intc 7>,
>                                               <&cpu34_intc 7>,
>                                               <&cpu35_intc 7>;
>                 };
>
> -               clint_mtimer9: timer@70ac090000 {
> +               clint_mtimer9: timer@70ac094000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu36_intc 7>,
>                                               <&cpu37_intc 7>,
>                                               <&cpu38_intc 7>,
>                                               <&cpu39_intc 7>;
>                 };
>
> -               clint_mtimer10: timer@70ac0a0000 {
> +               clint_mtimer10: timer@70ac0a4000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu40_intc 7>,
>                                               <&cpu41_intc 7>,
>                                               <&cpu42_intc 7>,
>                                               <&cpu43_intc 7>;
>                 };
>
> -               clint_mtimer11: timer@70ac0b0000 {
> +               clint_mtimer11: timer@70ac0b4000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu44_intc 7>,
>                                               <&cpu45_intc 7>,
>                                               <&cpu46_intc 7>,
>                                               <&cpu47_intc 7>;
>                 };
>
> -               clint_mtimer12: timer@70ac0c0000 {
> +               clint_mtimer12: timer@70ac0c4000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu48_intc 7>,
>                                               <&cpu49_intc 7>,
>                                               <&cpu50_intc 7>,
>                                               <&cpu51_intc 7>;
>                 };
>
> -               clint_mtimer13: timer@70ac0d0000 {
> +               clint_mtimer13: timer@70ac0d4000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu52_intc 7>,
>                                               <&cpu53_intc 7>,
>                                               <&cpu54_intc 7>,
>                                               <&cpu55_intc 7>;
>                 };
>
> -               clint_mtimer14: timer@70ac0e0000 {
> +               clint_mtimer14: timer@70ac0e4000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu56_intc 7>,
>                                               <&cpu57_intc 7>,
>                                               <&cpu58_intc 7>,
>                                               <&cpu59_intc 7>;
>                 };
>
> -               clint_mtimer15: timer@70ac0f0000 {
> +               clint_mtimer15: timer@70ac0f4000 {
>                         compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> -                       reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
> +                       reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
> +                       reg-names = "mtimecmp";
>                         interrupts-extended = <&cpu60_intc 7>,
>                                               <&cpu61_intc 7>,
>                                               <&cpu62_intc 7>,
> --
> 2.43.0
>
Reviewed-by: Guo Ren <guoren@kernel.org>
Inochi Amaoto Jan. 22, 2024, 3:04 a.m. UTC | #2 
Hi Conor,

I have already noticed the binding is merged. But the dt patch is not,
I wonder if it is the time to merge this dt change?

Regards,
Inochi
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 93256540d078..ead1cc35d88b 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -93,144 +93,160 @@  clint_mswi: interrupt-controller@7094000000 {
 					      <&cpu63_intc 3>;
 		};

-		clint_mtimer0: timer@70ac000000 {
+		clint_mtimer0: timer@70ac004000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu0_intc 7>,
 					      <&cpu1_intc 7>,
 					      <&cpu2_intc 7>,
 					      <&cpu3_intc 7>;
 		};

-		clint_mtimer1: timer@70ac010000 {
+		clint_mtimer1: timer@70ac014000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu4_intc 7>,
 					      <&cpu5_intc 7>,
 					      <&cpu6_intc 7>,
 					      <&cpu7_intc 7>;
 		};

-		clint_mtimer2: timer@70ac020000 {
+		clint_mtimer2: timer@70ac024000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu8_intc 7>,
 					      <&cpu9_intc 7>,
 					      <&cpu10_intc 7>,
 					      <&cpu11_intc 7>;
 		};

-		clint_mtimer3: timer@70ac030000 {
+		clint_mtimer3: timer@70ac034000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu12_intc 7>,
 					      <&cpu13_intc 7>,
 					      <&cpu14_intc 7>,
 					      <&cpu15_intc 7>;
 		};

-		clint_mtimer4: timer@70ac040000 {
+		clint_mtimer4: timer@70ac044000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu16_intc 7>,
 					      <&cpu17_intc 7>,
 					      <&cpu18_intc 7>,
 					      <&cpu19_intc 7>;
 		};

-		clint_mtimer5: timer@70ac050000 {
+		clint_mtimer5: timer@70ac054000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu20_intc 7>,
 					      <&cpu21_intc 7>,
 					      <&cpu22_intc 7>,
 					      <&cpu23_intc 7>;
 		};

-		clint_mtimer6: timer@70ac060000 {
+		clint_mtimer6: timer@70ac064000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu24_intc 7>,
 					      <&cpu25_intc 7>,
 					      <&cpu26_intc 7>,
 					      <&cpu27_intc 7>;
 		};

-		clint_mtimer7: timer@70ac070000 {
+		clint_mtimer7: timer@70ac074000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu28_intc 7>,
 					      <&cpu29_intc 7>,
 					      <&cpu30_intc 7>,
 					      <&cpu31_intc 7>;
 		};

-		clint_mtimer8: timer@70ac080000 {
+		clint_mtimer8: timer@70ac084000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu32_intc 7>,
 					      <&cpu33_intc 7>,
 					      <&cpu34_intc 7>,
 					      <&cpu35_intc 7>;
 		};

-		clint_mtimer9: timer@70ac090000 {
+		clint_mtimer9: timer@70ac094000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu36_intc 7>,
 					      <&cpu37_intc 7>,
 					      <&cpu38_intc 7>,
 					      <&cpu39_intc 7>;
 		};

-		clint_mtimer10: timer@70ac0a0000 {
+		clint_mtimer10: timer@70ac0a4000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu40_intc 7>,
 					      <&cpu41_intc 7>,
 					      <&cpu42_intc 7>,
 					      <&cpu43_intc 7>;
 		};

-		clint_mtimer11: timer@70ac0b0000 {
+		clint_mtimer11: timer@70ac0b4000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu44_intc 7>,
 					      <&cpu45_intc 7>,
 					      <&cpu46_intc 7>,
 					      <&cpu47_intc 7>;
 		};

-		clint_mtimer12: timer@70ac0c0000 {
+		clint_mtimer12: timer@70ac0c4000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu48_intc 7>,
 					      <&cpu49_intc 7>,
 					      <&cpu50_intc 7>,
 					      <&cpu51_intc 7>;
 		};

-		clint_mtimer13: timer@70ac0d0000 {
+		clint_mtimer13: timer@70ac0d4000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu52_intc 7>,
 					      <&cpu53_intc 7>,
 					      <&cpu54_intc 7>,
 					      <&cpu55_intc 7>;
 		};

-		clint_mtimer14: timer@70ac0e0000 {
+		clint_mtimer14: timer@70ac0e4000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu56_intc 7>,
 					      <&cpu57_intc 7>,
 					      <&cpu58_intc 7>,
 					      <&cpu59_intc 7>;
 		};

-		clint_mtimer15: timer@70ac0f0000 {
+		clint_mtimer15: timer@70ac0f4000 {
 			compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
-			reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
+			reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
+			reg-names = "mtimecmp";
 			interrupts-extended = <&cpu60_intc 7>,
 					      <&cpu61_intc 7>,
 					      <&cpu62_intc 7>,