| Message ID | 20240110-eastward-sulfide-f365c89681e0@spud (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: support new isa extension detection devicetree properties | expand |
On Wed, Jan 10, 2024 at 10:25:36AM +0000, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > A cpu may not have the same xlen as the compile time target, and > misa_mxl_max is the source of truth for what the hart supports. > > Reported-by: Andrew Jones <ajones@ventanamicro.com> > Link: https://lore.kernel.org/qemu-riscv/20240108-efa3f83dcd3997dc0af458d7@orel/ > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > Perhaps this misa_mxl_max -> width conversion should exist as a macro? > There's now 3 individual conversions of this type - two I added and one > in the gdb code. A macro is a good idea. I had to go look at Table 3.1 of the priv spec to understand the 16 shift stuff. > --- > target/riscv/cpu.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 8cbfc7e781..5b5da970f2 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1860,7 +1860,9 @@ char *riscv_isa_string(RISCVCPU *cpu) > int i; > const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); > char *isa_str = g_new(char, maxlen); > - char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); > + int xlen = 16 << cpu->env.misa_mxl_max; > + char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", xlen); > + > for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { > if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { > *p++ = qemu_tolower(riscv_single_letter_exts[i]); > -- > 2.39.2 > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
On Wed, Jan 10, 2024 at 9:34 PM Conor Dooley <conor@kernel.org> wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > A cpu may not have the same xlen as the compile time target, and > misa_mxl_max is the source of truth for what the hart supports. > > Reported-by: Andrew Jones <ajones@ventanamicro.com> > Link: https://lore.kernel.org/qemu-riscv/20240108-efa3f83dcd3997dc0af458d7@orel/ > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > Perhaps this misa_mxl_max -> width conversion should exist as a macro? > There's now 3 individual conversions of this type - two I added and one > in the gdb code. > --- > target/riscv/cpu.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 8cbfc7e781..5b5da970f2 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1860,7 +1860,9 @@ char *riscv_isa_string(RISCVCPU *cpu) > int i; > const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); > char *isa_str = g_new(char, maxlen); > - char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); > + int xlen = 16 << cpu->env.misa_mxl_max; > + char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", xlen); > + > for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { > if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { > *p++ = qemu_tolower(riscv_single_letter_exts[i]); > -- > 2.39.2 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbfc7e781..5b5da970f2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1860,7 +1860,9 @@ char *riscv_isa_string(RISCVCPU *cpu) int i; const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); char *isa_str = g_new(char, maxlen); - char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); + int xlen = 16 << cpu->env.misa_mxl_max; + char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", xlen); + for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { *p++ = qemu_tolower(riscv_single_letter_exts[i]);