| Message ID | 20240110-mold-renovate-256db1b5c70e@spud (mailing list archive) |
|---|---|
| Headers | show |
| Series | riscv: support new isa extension detection devicetree properties | expand |
On Wed, Jan 10, 2024 at 8:27 PM Conor Dooley <conor@kernel.org> wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > Making it a series to keep the standalone change to riscv_isa_string() > that Drew reported separate. > > Changes in v3: > - g_free() isa_extensions too > - use misa_mxl_max rather than the compile target for the base isa > - add a new patch changing riscv_isa_string() to do the same > - drop a null check that cannot be null > - rebased on top of Alistair's next branch Do you mind rebasing on https://github.com/alistair23/qemu/tree/riscv-to-apply.next again? There was a big re-org recently so lots of rebasing is required Alistair > > Changes in v2: > - use g_strdup() for multiletter extension string copying > - wrap stuff in #ifndef to prevent breaking the user mode build > - rename riscv_isa_set_props() -> riscv_isa_write_fdt() > > CC: Alistair Francis <Alistair.Francis@wdc.com> > CC: Bin Meng <bin.meng@windriver.com> > CC: Palmer Dabbelt <palmer@dabbelt.com> > CC: Weiwei Li <liwei1518@gmail.com> > CC: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > CC: Andrew Jones <ajones@ventanamicro.com> > CC: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> > CC: qemu-riscv@nongnu.org > CC: qemu-devel@nongnu.org > > Conor Dooley (2): > target/riscv: use misa_mxl_max to populate isa string rather than > TARGET_LONG_BITS > target/riscv: support new isa extension detection devicetree > properties > > hw/riscv/sifive_u.c | 7 ++---- > hw/riscv/spike.c | 6 ++--- > hw/riscv/virt.c | 6 ++--- > target/riscv/cpu.c | 57 ++++++++++++++++++++++++++++++++++++++++++++- > target/riscv/cpu.h | 1 + > 5 files changed, 63 insertions(+), 14 deletions(-) > > -- > 2.39.2 > >
On Mon, Jan 22, 2024 at 03:24:19PM +1000, Alistair Francis wrote: > On Wed, Jan 10, 2024 at 8:27 PM Conor Dooley <conor@kernel.org> wrote: > > > > From: Conor Dooley <conor.dooley@microchip.com> > > > > Making it a series to keep the standalone change to riscv_isa_string() > > that Drew reported separate. > > > > Changes in v3: > > - g_free() isa_extensions too > > - use misa_mxl_max rather than the compile target for the base isa > > - add a new patch changing riscv_isa_string() to do the same > > - drop a null check that cannot be null > > - rebased on top of Alistair's next branch > > Do you mind rebasing on > https://github.com/alistair23/qemu/tree/riscv-to-apply.next again? > There was a big re-org recently so lots of rebasing is required I can, sure. Do you want me to introduce the macro that I mentioned in the first patch as a helper for misa_mxl_max -> width conversions when I do? Thanks, Conor.
On Mon, Jan 22, 2024 at 10:25 PM Conor Dooley <conor@kernel.org> wrote: > > On Mon, Jan 22, 2024 at 03:24:19PM +1000, Alistair Francis wrote: > > On Wed, Jan 10, 2024 at 8:27 PM Conor Dooley <conor@kernel.org> wrote: > > > > > > From: Conor Dooley <conor.dooley@microchip.com> > > > > > > Making it a series to keep the standalone change to riscv_isa_string() > > > that Drew reported separate. > > > > > > Changes in v3: > > > - g_free() isa_extensions too > > > - use misa_mxl_max rather than the compile target for the base isa > > > - add a new patch changing riscv_isa_string() to do the same > > > - drop a null check that cannot be null > > > - rebased on top of Alistair's next branch > > > > Do you mind rebasing on > > https://github.com/alistair23/qemu/tree/riscv-to-apply.next again? > > There was a big re-org recently so lots of rebasing is required > > I can, sure. Do you want me to introduce the macro that I mentioned in > the first patch as a helper for misa_mxl_max -> width conversions when I > do? Yes please! Alistair > > Thanks, > Conor.
From: Conor Dooley <conor.dooley@microchip.com> Making it a series to keep the standalone change to riscv_isa_string() that Drew reported separate. Changes in v3: - g_free() isa_extensions too - use misa_mxl_max rather than the compile target for the base isa - add a new patch changing riscv_isa_string() to do the same - drop a null check that cannot be null - rebased on top of Alistair's next branch Changes in v2: - use g_strdup() for multiletter extension string copying - wrap stuff in #ifndef to prevent breaking the user mode build - rename riscv_isa_set_props() -> riscv_isa_write_fdt() CC: Alistair Francis <Alistair.Francis@wdc.com> CC: Bin Meng <bin.meng@windriver.com> CC: Palmer Dabbelt <palmer@dabbelt.com> CC: Weiwei Li <liwei1518@gmail.com> CC: Daniel Henrique Barboza <dbarboza@ventanamicro.com> CC: Andrew Jones <ajones@ventanamicro.com> CC: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> CC: qemu-riscv@nongnu.org CC: qemu-devel@nongnu.org Conor Dooley (2): target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS target/riscv: support new isa extension detection devicetree properties hw/riscv/sifive_u.c | 7 ++---- hw/riscv/spike.c | 6 ++--- hw/riscv/virt.c | 6 ++--- target/riscv/cpu.c | 57 ++++++++++++++++++++++++++++++++++++++++++++- target/riscv/cpu.h | 1 + 5 files changed, 63 insertions(+), 14 deletions(-)