| Message ID | 20240118220243.203655-1-marex@denx.de (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | drm/bridge: tc358767: Limit the Pixel PLL input range | expand |
Am Donnerstag, dem 18.01.2024 um 23:02 +0100 schrieb Marek Vasut: > According to new configuration spreadsheet from Toshiba for TC9595, > the Pixel PLL input clock have to be in range 6..40 MHz. The sheet > calculates those PLL input clock as reference clock divided by both > pre-dividers. Add the extra limit. > > Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > --- > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > Cc: Daniel Vetter <daniel@ffwll.ch> > Cc: David Airlie <airlied@gmail.com> > Cc: Jernej Skrabec <jernej.skrabec@gmail.com> > Cc: Jonas Karlman <jonas@kwiboo.se> > Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: Neil Armstrong <neil.armstrong@linaro.org> > Cc: Robert Foss <rfoss@kernel.org> > Cc: dri-devel@lists.freedesktop.org > --- > drivers/gpu/drm/bridge/tc358767.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c > index 615cc8f950d7b..0c29a8f81cc9e 100644 > --- a/drivers/gpu/drm/bridge/tc358767.c > +++ b/drivers/gpu/drm/bridge/tc358767.c > @@ -546,9 +546,14 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) > continue; > for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) { > for (div = 1; div <= 16; div++) { > - u32 clk; > + u32 clk, iclk; > u64 tmp; > > + /* PCLK PLL input unit clock ... 6..40 MHz */ > + iclk = refclk / (div * ext_div[i_pre]); > + if (iclk < 6000000 || iclk > 40000000) > + continue; > + > tmp = pixelclock * ext_div[i_pre] * > ext_div[i_post] * div; > do_div(tmp, refclk);
On Thu, 18 Jan 2024 23:02:31 +0100, Marek Vasut wrote: > According to new configuration spreadsheet from Toshiba for TC9595, > the Pixel PLL input clock have to be in range 6..40 MHz. The sheet > calculates those PLL input clock as reference clock divided by both > pre-dividers. Add the extra limit. > > Applied, thanks! [1/1] drm/bridge: tc358767: Limit the Pixel PLL input range https://cgit.freedesktop.org/drm/drm-misc/commit/?id=f86ae204bec4 Rob
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 615cc8f950d7b..0c29a8f81cc9e 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -546,9 +546,14 @@ static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) continue; for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) { for (div = 1; div <= 16; div++) { - u32 clk; + u32 clk, iclk; u64 tmp; + /* PCLK PLL input unit clock ... 6..40 MHz */ + iclk = refclk / (div * ext_div[i_pre]); + if (iclk < 6000000 || iclk > 40000000) + continue; + tmp = pixelclock * ext_div[i_pre] * ext_div[i_post] * div; do_div(tmp, refclk);
According to new configuration spreadsheet from Toshiba for TC9595, the Pixel PLL input clock have to be in range 6..40 MHz. The sheet calculates those PLL input clock as reference clock divided by both pre-dividers. Add the extra limit. Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Andrzej Hajda <andrzej.hajda@intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: David Airlie <airlied@gmail.com> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: Jonas Karlman <jonas@kwiboo.se> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Neil Armstrong <neil.armstrong@linaro.org> Cc: Robert Foss <rfoss@kernel.org> Cc: dri-devel@lists.freedesktop.org --- drivers/gpu/drm/bridge/tc358767.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)