| Message ID | 20240108205140.1701770-1-horatiu.vultur@microchip.com |
|---|---|
| State | Accepted |
| Commit | 4e4a1183f281d95fbb6caf28d670775d13264beb |
| Headers | show |
| Series | phy: lan966x: Add missing serdes mux entry | expand |
On Mon, 08 Jan 2024 21:51:40 +0100, Horatiu Vultur wrote: > According to the datasheet(Table 3-2: Port configuration) the serdes 2 > (SD2) can be configured to run QSGMII or SGMII mode. Already the QSGMII > mode is supported in the serdes_muxes list but was missing the SGMII mode. > In this mode the serdes is connected to the port 4. > Therefore add this entry in the list. > > > [...] Applied, thanks! [1/1] phy: lan966x: Add missing serdes mux entry commit: 4e4a1183f281d95fbb6caf28d670775d13264beb Best regards,
diff --git a/drivers/phy/microchip/lan966x_serdes.c b/drivers/phy/microchip/lan966x_serdes.c index c1a41b6cd29b1..b5ac2b7995e71 100644 --- a/drivers/phy/microchip/lan966x_serdes.c +++ b/drivers/phy/microchip/lan966x_serdes.c @@ -96,6 +96,8 @@ static const struct serdes_mux lan966x_serdes_muxes[] = { SERDES_MUX_SGMII(SERDES6G(1), 3, HSIO_HW_CFG_SD6G_1_CFG, HSIO_HW_CFG_SD6G_1_CFG_SET(1)), + SERDES_MUX_SGMII(SERDES6G(2), 4, 0, 0), + SERDES_MUX_RGMII(RGMII(0), 2, HSIO_HW_CFG_RGMII_0_CFG | HSIO_HW_CFG_RGMII_ENA | HSIO_HW_CFG_GMII_ENA,
According to the datasheet(Table 3-2: Port configuration) the serdes 2 (SD2) can be configured to run QSGMII or SGMII mode. Already the QSGMII mode is supported in the serdes_muxes list but was missing the SGMII mode. In this mode the serdes is connected to the port 4. Therefore add this entry in the list. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> --- drivers/phy/microchip/lan966x_serdes.c | 2 ++ 1 file changed, 2 insertions(+)