| Message ID | 20240124-pcie-aux-clk-fix-v1-12-d8a4852b6ba6@linaro.org |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | Drop PCIE_AUX_CLK from the PCIe PHY nodes of Qcom SoCs | expand |
On 24/01/2024 08:36, Manivannan Sadhasivam wrote: > PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is > only required by the PCIe controller. Hence drop it from pcie_phy node. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index ee1ba5a8c8fc..f074683f7940 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -1760,13 +1760,11 @@ pcie0_phy: phy@1c06000 { > compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; > reg = <0 0x01c06000 0 0x2000>; > > - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, > - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > <&tcsr TCSR_PCIE_0_CLKREF_EN>, > <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, > <&gcc GCC_PCIE_0_PIPE_CLK>; > - clock-names = "aux", "cfg_ahb", "ref", "rchng", > - "pipe"; > + clock-names = "cfg_ahb", "ref", "rchng", "pipe"; > > resets = <&gcc GCC_PCIE_0_PHY_BCR>; > reset-names = "phy"; > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee1ba5a8c8fc..f074683f7940 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1760,13 +1760,11 @@ pcie0_phy: phy@1c06000 { compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; reg = <0 0x01c06000 0 0x2000>; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&tcsr TCSR_PCIE_0_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", - "pipe"; + clock-names = "cfg_ahb", "ref", "rchng", "pipe"; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy";
PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is only required by the PCIe controller. Hence drop it from pcie_phy node. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)