| Message ID | 20240124213640.7582-2-ansuelsmth@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | net: mdio-ipq4019: fix wrong default MDC rate | expand |
> + clock-frequency: > + description: > + The MDIO bus clock that must be output by the MDIO bus hardware, if > + absent, the default hardware values are used. > + > + MDC rate is feed by an external clock (fixed 100MHz) and is divider > + internally. The default divider is /256 resulting in the default rate > + applied of 390KHz. > + enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ] Hi Christian 802.3 says the clock should be up to 2.5MHz by default. So the nearest would be 1562500. Please document that if not set, it defaults to this. And make the driver actually default to that. Andrew
On Wed, Jan 24, 2024 at 11:23:05PM +0100, Andrew Lunn wrote: > > + clock-frequency: > > + description: > > + The MDIO bus clock that must be output by the MDIO bus hardware, if > > + absent, the default hardware values are used. > > + > > + MDC rate is feed by an external clock (fixed 100MHz) and is divider > > + internally. The default divider is /256 resulting in the default rate > > + applied of 390KHz. > > + enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ] > > Hi Christian > > 802.3 says the clock should be up to 2.5MHz by default. So the nearest > would be 1562500. Please document that if not set, it defaults to > this. And make the driver actually default to that. > As I said, this is very fk up and default value is 390KHz unless anyone in the chain sets it (sometime uboot does it but it's not that common... default qsdk uboot doesn't do that for example)... Ok I have to change this to default to 1562500.
On Wed, Jan 24, 2024 at 11:27:20PM +0100, Christian Marangi wrote: > On Wed, Jan 24, 2024 at 11:23:05PM +0100, Andrew Lunn wrote: > > > + clock-frequency: > > > + description: > > > + The MDIO bus clock that must be output by the MDIO bus hardware, if > > > + absent, the default hardware values are used. > > > + > > > + MDC rate is feed by an external clock (fixed 100MHz) and is divider > > > + internally. The default divider is /256 resulting in the default rate > > > + applied of 390KHz. > > > + enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ] > > > > Hi Christian > > > > 802.3 says the clock should be up to 2.5MHz by default. So the nearest > > would be 1562500. Please document that if not set, it defaults to > > this. And make the driver actually default to that. > > > > As I said, this is very fk up and default value is 390KHz unless anyone > in the chain sets it (sometime uboot does it but it's not that common... > default qsdk uboot doesn't do that for example)... Ok I have to change > this to default to 1562500. I doubt you will cause any regression by defaulting to 2.5HHz instead. That is what the standard says it should be. All devices on the bus should support that. Andrew
On 24/01/2024 22:36, Christian Marangi wrote: > Document support for clock-frequency and add details on why this > property is needed and what values are supported. ... > + clock-frequency: > + description: > + The MDIO bus clock that must be output by the MDIO bus hardware, if > + absent, the default hardware values are used. > + > + MDC rate is feed by an external clock (fixed 100MHz) and is divider > + internally. The default divider is /256 resulting in the default rate > + applied of 390KHz. > + enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ] default: 390625 Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml index 3407e909e8a7..603dbfb95ac9 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml @@ -44,6 +44,16 @@ properties: items: - const: gcc_mdio_ahb_clk + clock-frequency: + description: + The MDIO bus clock that must be output by the MDIO bus hardware, if + absent, the default hardware values are used. + + MDC rate is feed by an external clock (fixed 100MHz) and is divider + internally. The default divider is /256 resulting in the default rate + applied of 390KHz. + enum: [ 390625, 781250, 1562500, 3125000, 6250000, 12500000 ] + required: - compatible - reg
Document support for clock-frequency and add details on why this property is needed and what values are supported. From internal documentation, while other values are supported, the correct function of the MDIO bus is not assured hence add only the suggested supported values to the property enum. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> --- .../devicetree/bindings/net/qcom,ipq4019-mdio.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+)