[2/3] dt-bindings: phy: Add Rockchip HDMI/DP Combo PHY schema

Commit Message

Cristian Ciocaltea Jan. 19, 2024, 7:38 p.m. UTC

Add dt-binding schema for the Rockchip HDMI/DP Transmitter Combo PHY
found on RK3588 SoC.

Signed-off-by: Cristian Ciocaltea <[e-mail]>
---
 .../phy/rockchip,rk3588-hdptx-phy.yaml        | 96 +++++++++++++++++++
 1 file changed, 96 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml

Comments

Krzysztof Kozlowski Jan. 25, 2024, 9:11 a.m. UTC | #1

On 19/01/2024 20:38, Cristian Ciocaltea wrote:
> +    soc {
> +      #address-cells = <2>;
> +      #size-cells = <2>;
> +
> +      hdptxphy_grf: syscon@fd5e0000 {
> +        compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
> +        reg = <0x0 0xfd5e0000 0x0 0x100>;
> +      };

Drop node, not part of this binding.

> +
> +      hdptxphy: phy@fed60000 {

Drop label.

> +        compatible = "rockchip,rk3588-hdptx-phy";
> +        reg = <0x0 0xfed60000 0x0 0x2000>;
> +        clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
> +        clock-names = "ref", "apb";

With these two changes:

Reviewed-by: Krzysztof Kozlowski <[e-mail]>

Best regards,
Krzysztof

Cristian Ciocaltea Jan. 25, 2024, 9:39 a.m. UTC | #2

On 1/25/24 11:11, Krzysztof Kozlowski wrote:
> On 19/01/2024 20:38, Cristian Ciocaltea wrote:
>> +    soc {
>> +      #address-cells = <2>;
>> +      #size-cells = <2>;
>> +
>> +      hdptxphy_grf: syscon@fd5e0000 {
>> +        compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
>> +        reg = <0x0 0xfd5e0000 0x0 0x100>;
>> +      };
> 
> Drop node, not part of this binding.
> 
>> +
>> +      hdptxphy: phy@fed60000 {
> 
> Drop label.
> 
>> +        compatible = "rockchip,rk3588-hdptx-phy";
>> +        reg = <0x0 0xfed60000 0x0 0x2000>;
>> +        clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
>> +        clock-names = "ref", "apb";
> 
> With these two changes:
> 
> Reviewed-by: Krzysztof Kozlowski <[e-mail]>

Will do, thanks for the review!

Regards,
Cristian

Patch

diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml
new file mode 100644
index 000000000000..dd357994ba1b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml
@@ -0,0 +1,96 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC HDMI/DP Transmitter Combo PHY
+
+maintainers:
+  - Cristian Ciocaltea <[e-mail]>
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rk3588-hdptx-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Reference clock
+      - description: APB clock
+
+  clock-names:
+    items:
+      - const: ref
+      - const: apb
+
+  "#phy-cells":
+    const: 0
+
+  resets:
+    items:
+      - description: PHY reset line
+      - description: APB reset line
+      - description: INIT reset line
+      - description: CMN reset line
+      - description: LANE reset line
+      - description: ROPLL reset line
+      - description: LCPLL reset line
+
+  reset-names:
+    items:
+      - const: phy
+      - const: apb
+      - const: init
+      - const: cmn
+      - const: lane
+      - const: ropll
+      - const: lcpll
+
+  rockchip,grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: Some PHY related data is accessed through GRF regs.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#phy-cells"
+  - resets
+  - reset-names
+  - rockchip,grf
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      hdptxphy_grf: syscon@fd5e0000 {
+        compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
+        reg = <0x0 0xfd5e0000 0x0 0x100>;
+      };
+
+      hdptxphy: phy@fed60000 {
+        compatible = "rockchip,rk3588-hdptx-phy";
+        reg = <0x0 0xfed60000 0x0 0x2000>;
+        clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
+        clock-names = "ref", "apb";
+        #phy-cells = <0>;
+        resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
+                 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
+                 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
+                 <&cru SRST_HDPTX0_LCPLL>;
+        reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
+        rockchip,grf = <&hdptxphy_grf>;
+      };
+    };