| Message ID | 20240127003607.501086-5-andre.draszik@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/5] clk: samsung: gs101: gpio_peric0_pclk needs to be kept on | expand |
On Sat, 2024-01-27 at 00:35 +0000, André Draszik wrote:
> Wrong pclk clocks have been used in this usi8 instance here. For USI
^^^^
This should read 'uart', I'll send a v2 after collecting any other potential
feedback.
Cheers,
Andre'
On Fri, Jan 26, 2024 at 6:37 PM André Draszik <andre.draszik@linaro.org> wrote: > > Wrong pclk clocks have been used in this usi8 instance here. For USI > and UART, we need the ipclk and pclk, where pclk is the bus clock. > Without it, nothing can work. Missing empty line? > It is unclear what exactly is using USI0_UART_CLK, but it is not > required for the IP to be operational at this stage, while pclk is. > This also brings the DT in line with the clock names expected by the > usi and uart drivers. > > Update the DTSI accordingly. > > Fixes: d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") > Signed-off-by: André Draszik <andre.draszik@linaro.org> > --- Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > index e5b665be2d62..f93e937d2726 100644 > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -410,7 +410,7 @@ usi_uart: usi@10a000c0 { > ranges; > #address-cells = <1>; > #size-cells = <1>; > - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, > + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, > <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; > clock-names = "pclk", "ipclk"; > samsung,sysreg = <&sysreg_peric0 0x1020>; > @@ -422,7 +422,7 @@ serial_0: serial@10a00000 { > reg = <0x10a00000 0xc0>; > interrupts = <GIC_SPI 634 > IRQ_TYPE_LEVEL_HIGH 0>; > - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, > + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, > <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; > clock-names = "uart", "clk_uart_baud0"; > samsung,uart-fifosize = <256>; > -- > 2.43.0.429.g432eaa2c6b-goog >
On 1/27/24 00:35, André Draszik wrote: > Wrong pclk clocks have been used in this usi8 instance here. For USI > and UART, we need the ipclk and pclk, where pclk is the bus clock. > Without it, nothing can work. > It is unclear what exactly is using USI0_UART_CLK, but it is not > required for the IP to be operational at this stage, while pclk is. > This also brings the DT in line with the clock names expected by the > usi and uart drivers. > > Update the DTSI accordingly. > > Fixes: d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") > Signed-off-by: André Draszik <andre.draszik@linaro.org> > --- > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > index e5b665be2d62..f93e937d2726 100644 > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -410,7 +410,7 @@ usi_uart: usi@10a000c0 { > ranges; > #address-cells = <1>; > #size-cells = <1>; > - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, > + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, As I said in the previous email, I don't think this is correct. This is just a heads up for Krzysztof to not pick these 2 patches yet. We'll come back on this matter on Monday. > <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; > clock-names = "pclk", "ipclk"; > samsung,sysreg = <&sysreg_peric0 0x1020>; > @@ -422,7 +422,7 @@ serial_0: serial@10a00000 { > reg = <0x10a00000 0xc0>; > interrupts = <GIC_SPI 634 > IRQ_TYPE_LEVEL_HIGH 0>; > - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, > + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, > <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; > clock-names = "uart", "clk_uart_baud0"; > samsung,uart-fifosize = <256>;
On 1/27/24 04:03, Tudor Ambarus wrote: > We'll > come back on this matter on Monday. I tested (correctly this time) and the patch is good: Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Tested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index e5b665be2d62..f93e937d2726 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -410,7 +410,7 @@ usi_uart: usi@10a000c0 { ranges; #address-cells = <1>; #size-cells = <1>; - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1020>; @@ -422,7 +422,7 @@ serial_0: serial@10a00000 { reg = <0x10a00000 0xc0>; interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>, + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>;
Wrong pclk clocks have been used in this usi8 instance here. For USI and UART, we need the ipclk and pclk, where pclk is the bus clock. Without it, nothing can work. It is unclear what exactly is using USI0_UART_CLK, but it is not required for the IP to be operational at this stage, while pclk is. This also brings the DT in line with the clock names expected by the usi and uart drivers. Update the DTSI accordingly. Fixes: d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") Signed-off-by: André Draszik <andre.draszik@linaro.org> --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)