| Message ID | IA1PR20MB4953654F150743B649D5ADCEBB7E2@IA1PR20MB4953.namprd20.prod.outlook.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | riscv: sophgo: add i2c and spi device to CV180x/SG2000x SoCs | expand |
Hi Inochi Amaoto On 10:26 Mon 29 Jan , Inochi Amaoto wrote: > Add spi devices for the CV180x, CV181x and SG200x soc. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > --- > arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 44 ++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > index 7c88cbe8e91d..e66f9e9feb48 100644 > --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > @@ -176,6 +176,50 @@ uart3: serial@4170000 { > status = "disabled"; > }; > > + spi0: spi@4180000 { > + compatible = "snps,dw-apb-ssi"; > + reg = <0x04180000 0x10000>; > + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; > + clock-names = "ssi_clk", "pclk"; .. > + #address-cells = <1>; > + #size-cells = <0>; I'd suggest moving those two above 'interrupts' property there is an ongoing discussion here.. https://lore.kernel.org/all/20231203174622.18402-1-krzysztof.kozlowski@linaro.org/ > + status = "disabled"; > + }; > + > + spi1: spi@4190000 { > + compatible = "snps,dw-apb-ssi"; > + reg = <0x04190000 0x10000>; > + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; > + clock-names = "ssi_clk", "pclk"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi2: spi@41a0000 { > + compatible = "snps,dw-apb-ssi"; > + reg = <0x041a0000 0x10000>; > + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; > + clock-names = "ssi_clk", "pclk"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi3: spi@41b0000 { > + compatible = "snps,dw-apb-ssi"; > + reg = <0x041b0000 0x10000>; > + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; > + clock-names = "ssi_clk", "pclk"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > uart4: serial@41c0000 { > compatible = "snps,dw-apb-uart"; > reg = <0x041c0000 0x100>; > -- > 2.43.0
>Hi Inochi Amaoto > >On 10:26 Mon 29 Jan , Inochi Amaoto wrote: >> Add spi devices for the CV180x, CV181x and SG200x soc. >> >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> >> --- >> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 44 ++++++++++++++++++++++++++ >> 1 file changed, 44 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi >> index 7c88cbe8e91d..e66f9e9feb48 100644 >> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi >> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi >> @@ -176,6 +176,50 @@ uart3: serial@4170000 { >> status = "disabled"; >> }; >> >> + spi0: spi@4180000 { >> + compatible = "snps,dw-apb-ssi"; >> + reg = <0x04180000 0x10000>; >> + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; >> + clock-names = "ssi_clk", "pclk"; >.. >> + #address-cells = <1>; >> + #size-cells = <0>; >I'd suggest moving those two above 'interrupts' property > >there is an ongoing discussion here.. >https://lore.kernel.org/all/20231203174622.18402-1-krzysztof.kozlowski@linaro.org/ > Thanks for this info. I will take care of it. >> + status = "disabled"; >> + }; >> + >> + spi1: spi@4190000 { >> + compatible = "snps,dw-apb-ssi"; >> + reg = <0x04190000 0x10000>; >> + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; >> + clock-names = "ssi_clk", "pclk"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi2: spi@41a0000 { >> + compatible = "snps,dw-apb-ssi"; >> + reg = <0x041a0000 0x10000>; >> + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; >> + clock-names = "ssi_clk", "pclk"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> + spi3: spi@41b0000 { >> + compatible = "snps,dw-apb-ssi"; >> + reg = <0x041b0000 0x10000>; >> + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; >> + clock-names = "ssi_clk", "pclk"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "disabled"; >> + }; >> + >> uart4: serial@41c0000 { >> compatible = "snps,dw-apb-uart"; >> reg = <0x041c0000 0x100>; >> -- >> 2.43.0 > >-- >Yixun Lan (dlan) >Gentoo Linux Developer >GPG Key ID AABEFD55
On Mon, Jan 29, 2024 at 11:47:18AM +0800, Inochi Amaoto wrote: > >Hi Inochi Amaoto > > > >On 10:26 Mon 29 Jan , Inochi Amaoto wrote: > >> Add spi devices for the CV180x, CV181x and SG200x soc. > >> > >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > >> --- > >> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 44 ++++++++++++++++++++++++++ > >> 1 file changed, 44 insertions(+) > >> > >> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > >> index 7c88cbe8e91d..e66f9e9feb48 100644 > >> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > >> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > >> @@ -176,6 +176,50 @@ uart3: serial@4170000 { > >> status = "disabled"; > >> }; > >> > >> + spi0: spi@4180000 { > >> + compatible = "snps,dw-apb-ssi"; > >> + reg = <0x04180000 0x10000>; > >> + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; > >> + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; > >> + clock-names = "ssi_clk", "pclk"; > >.. > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >I'd suggest moving those two above 'interrupts' property > > > >there is an ongoing discussion here.. Not super important to point out, but this discussion isn't "ongoing", it was merged into 6.8-rc1: https://docs.kernel.org/devicetree/bindings/dts-coding-style.html Cheers, Conor. > >https://lore.kernel.org/all/20231203174622.18402-1-krzysztof.kozlowski@linaro.org/ > > > > Thanks for this info. I will take care of it.
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 7c88cbe8e91d..e66f9e9feb48 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -176,6 +176,50 @@ uart3: serial@4170000 { status = "disabled"; }; + spi0: spi@4180000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x04180000 0x10000>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; + clock-names = "ssi_clk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4190000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x04190000 0x10000>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; + clock-names = "ssi_clk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@41a0000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x041a0000 0x10000>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; + clock-names = "ssi_clk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@41b0000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x041b0000 0x10000>; + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; + clock-names = "ssi_clk", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart4: serial@41c0000 { compatible = "snps,dw-apb-uart"; reg = <0x041c0000 0x100>;
Add spi devices for the CV180x, CV181x and SG200x soc. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> --- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 44 ++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) -- 2.43.0