diff mbox series

[v6,4/4] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property

Message ID 20240129135556.63466-5-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Accepted
Delegated to: Geert Uytterhoeven
Headers show
Series Add missing port pins on RZ/Five SoC | expand

Commit Message

Lad, Prabhakar Jan. 29, 2024, 1:55 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update
the gpio-ranges property in RZ/Five SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Geert Uytterhoeven Jan. 30, 2024, 10:38 a.m. UTC | #1 
On Mon, Jan 29, 2024 at 2:56 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update
> the gpio-ranges property in RZ/Five SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl for v6.10, as this has a hard
dependency on the pin control patches.

Gr{oetje,eeting}s,

                        Geert
Geert Uytterhoeven Jan. 31, 2024, 1:48 p.m. UTC | #2 
Hi Prabhakar,

On Tue, Jan 30, 2024 at 11:38 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Mon, Jan 29, 2024 at 2:56 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update
> > the gpio-ranges property in RZ/Five SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in renesas-pinctrl for v6.10, as this has a hard
> dependency on the pin control patches.

It's worse: the pin control patches without the DT patch breaks, soo.
So I have no choice but merging patch 3/4 and 4/4.

Gr{oetje,eeting}s,

                        Geert
Lad, Prabhakar Jan. 31, 2024, 2:39 p.m. UTC | #3 
Hi Geert,

On Wed, Jan 31, 2024 at 1:49 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, Jan 30, 2024 at 11:38 AM Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
> > On Mon, Jan 29, 2024 at 2:56 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update
> > > the gpio-ranges property in RZ/Five SoC DTSI.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > i.e. will queue in renesas-pinctrl for v6.10, as this has a hard
> > dependency on the pin control patches.
>
> It's worse: the pin control patches without the DT patch breaks, soo.
> So I have no choice but merging patch 3/4 and 4/4.
>
Fine by me.

Cheers,
Prabhakar
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index d2272a0bfb61..aa3b1d2b999d 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -46,6 +46,10 @@  cpu0_intc: interrupt-controller {
 	};
 };
 
+&pinctrl {
+	gpio-ranges = <&pinctrl 0 0 232>;
+};
+
 &soc {
 	dma-noncoherent;
 	interrupt-parent = <&plic>;