| Message ID | 20240123082100.7334-2-zajec5@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | dt-bindings: arm: mediatek: convert MT7622-related bindings to the json-schema | expand |
On Tue, Jan 23, 2024 at 09:20:58AM +0100, Rafał Miłecki wrote: > From: Rafał Miłecki <rafal@milecki.pl> > > This helps validating DTS files. Introduced changes: > 1. Documented "reg" property > 2. Documented "#reset-cells" property > 3. Adjusted "reg" in example > > Signed-off-by: Rafał Miłecki <rafal@milecki.pl> > --- > .../bindings/arm/mediatek/mediatek,hifsys.txt | 26 --------- > .../arm/mediatek/mediatek,mt2701-hifsys.yaml | 54 +++++++++++++++++++ Like the other one, please move this. > 2 files changed, 54 insertions(+), 26 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt2701-hifsys.yaml > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt > deleted file mode 100644 > index 323905af82c3..000000000000 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt > +++ /dev/null > @@ -1,26 +0,0 @@ > -Mediatek hifsys controller > -============================ > - > -The Mediatek hifsys controller provides various clocks and reset > -outputs to the system. > - > -Required Properties: > - > -- compatible: Should be: > - - "mediatek,mt2701-hifsys", "syscon" > - - "mediatek,mt7622-hifsys", "syscon" > - - "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon" > -- #clock-cells: Must be 1 > - > -The hifsys controller uses the common clk binding from > -Documentation/devicetree/bindings/clock/clock-bindings.txt > -The available clocks are defined in dt-bindings/clock/mt*-clk.h. > - > -Example: > - > -hifsys: clock-controller@1a000000 { > - compatible = "mediatek,mt2701-hifsys", "syscon"; > - reg = <0 0x1a000000 0 0x1000>; > - #clock-cells = <1>; > - #reset-cells = <1>; > -}; > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt2701-hifsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt2701-hifsys.yaml > new file mode 100644 > index 000000000000..7c7b7b7b1142 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt2701-hifsys.yaml > @@ -0,0 +1,54 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt2701-hifsys.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek hifsys controller > + > +description: > + The Mediatek hifsys controller provides various clocks and reset outputs to > + the system. > + > +maintainers: > + - Matthias Brugger <matthias.bgg@gmail.com> > + > +properties: > + compatible: > + oneOf: > + - items: > + - const: mediatek,mt2701-hifsys > + - const: syscon > + - items: > + - enum: > + - mediatek,mt7623-hifsys > + - const: mediatek,mt2701-hifsys > + - const: syscon > + - items: > + - const: mediatek,mt7622-hifsys > + - const: syscon The 1st and 3rd entries can be combined. > + > + reg: > + maxItems: 1 > + > + "#clock-cells": > + const: 1 > + description: The available clocks are defined in dt-bindings/clock/mt*-clk.h > + > + "#reset-cells": > + const: 1 > + > +required: > + - reg > + - "#clock-cells" > + > +additionalProperties: false > + > +examples: > + - | > + clock-controller@1a000000 { > + compatible = "mediatek,mt2701-hifsys", "syscon"; > + reg = <0x1a000000 0x1000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > -- > 2.35.3 >
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt deleted file mode 100644 index 323905af82c3..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt +++ /dev/null @@ -1,26 +0,0 @@ -Mediatek hifsys controller -============================ - -The Mediatek hifsys controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt2701-hifsys", "syscon" - - "mediatek,mt7622-hifsys", "syscon" - - "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon" -- #clock-cells: Must be 1 - -The hifsys controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -hifsys: clock-controller@1a000000 { - compatible = "mediatek,mt2701-hifsys", "syscon"; - reg = <0 0x1a000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt2701-hifsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt2701-hifsys.yaml new file mode 100644 index 000000000000..7c7b7b7b1142 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt2701-hifsys.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt2701-hifsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek hifsys controller + +description: + The Mediatek hifsys controller provides various clocks and reset outputs to + the system. + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + +properties: + compatible: + oneOf: + - items: + - const: mediatek,mt2701-hifsys + - const: syscon + - items: + - enum: + - mediatek,mt7623-hifsys + - const: mediatek,mt2701-hifsys + - const: syscon + - items: + - const: mediatek,mt7622-hifsys + - const: syscon + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + description: The available clocks are defined in dt-bindings/clock/mt*-clk.h + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1a000000 { + compatible = "mediatek,mt2701-hifsys", "syscon"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + };