| Message ID | 20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Update SSI interrupts for RZ/G2L family and Split out RZ/G2UL DTS/I | expand |
Hi! > This patch series does the below, > - Updates SSI interrupts for RZ/G2L family > - Splits up RZ/G2UL DTS/I for re-using for RZ/Five SoC > > Note, patch #5 has been newly added and rest of the patches have been > cherry-picked from upstream kernel. I'll take more detailed look but just to be sure: do you plan to backport RISC-V changes to 5.10? If so, do you have some kind of WIP series, just to get an idea how big changes that means? Best regards, Pavel
Hi Pavel, > Hi! > > > This patch series does the below, > > - Updates SSI interrupts for RZ/G2L family > > - Splits up RZ/G2UL DTS/I for re-using for RZ/Five SoC > > > > Note, patch #5 has been newly added and rest of the patches have been > > cherry-picked from upstream kernel. > > I'll take more detailed look but just to be sure: do you plan to backport RISC-V changes to 5.10? If > so, do you have some kind of WIP series, just to get an idea how big changes that means? > I've already posted out an RFC series [0] adding support for RZ/Five RISC-V SoC to 5.10-cip. [0] https://patchwork.kernel.org/project/cip-dev/cover/20240130203346.94488-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Cheers, Prabhakar > Best regards, > Pavel > -- > DENX Software Engineering GmbH, Managing Director: Erika Unter > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Hi! > > > This patch series does the below, > > > - Updates SSI interrupts for RZ/G2L family > > > - Splits up RZ/G2UL DTS/I for re-using for RZ/Five SoC > > > > > > Note, patch #5 has been newly added and rest of the patches have been > > > cherry-picked from upstream kernel. > > > > I'll take more detailed look but just to be sure: do you plan to backport RISC-V changes to 5.10? If > > so, do you have some kind of WIP series, just to get an idea how big changes that means? > > > I've already posted out an RFC series [0] adding support for RZ/Five RISC-V SoC to 5.10-cip. > > [0] https://patchwork.kernel.org/project/cip-dev/cover/20240130203346.94488-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ Yep, sorry, I seen it shortly after sending the email, sorry for confusion. I went through the series. I'm okay with taking 1-4 (provided they pass testing and there are no other comments). I'd propose taking 5-9 after we decide to take the [0]. I'll take a short look at the series, but ultimately I believe we should talk about 5.10 RISC-V at the IRC meeting. Best regards, Pavel
Hi! > > > I'll take more detailed look but just to be sure: do you plan to backport RISC-V changes to 5.10? If > > > so, do you have some kind of WIP series, just to get an idea how big changes that means? > > > > > I've already posted out an RFC series [0] adding support for RZ/Five RISC-V SoC to 5.10-cip. > > > > [0] https://patchwork.kernel.org/project/cip-dev/cover/20240130203346.94488-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > > Yep, sorry, I seen it shortly after sending the email, sorry for > confusion. > > I went through the series. I'm okay with taking 1-4 (provided they > pass testing and there are no other comments). I applied patches 1-4. I propose we take the rest with the [0]. Best regards, Pavel
Hi All, This patch series does the below, - Updates SSI interrupts for RZ/G2L family - Splits up RZ/G2UL DTS/I for re-using for RZ/Five SoC Note, patch #5 has been newly added and rest of the patches have been cherry-picked from upstream kernel. Cheers, Prabhakar Lad Prabhakar (9): ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names properties ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts .../bindings/sound/renesas,rz-ssi.yaml | 21 +- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 350 ++++++++---------- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 72 ++++ .../boot/dts/renesas/r9a07g043u11-smarc.dts | 17 +- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 19 +- arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 14 - sound/soc/sh/rz-ssi.c | 63 +++- 8 files changed, 304 insertions(+), 271 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi