| Message ID | 20240130110945.486-1-zhiwei_liu@linux.alibaba.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: FCSR doesn't contain vxrm and vxsat | expand |
On 1/30/24 08:09, LIU Zhiwei wrote: > vxrm and vxsat have been moved into a special register vcsr since > RVV v1.0. So remove them from FCSR for vector 1.0. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu_bits.h | 8 -------- > 1 file changed, 8 deletions(-) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index ebd7917d49..e116f6c252 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -32,14 +32,6 @@ > #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) > #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) > > -/* Vector Fixed-Point round model */ > -#define FSR_VXRM_SHIFT 9 > -#define FSR_VXRM (0x3 << FSR_VXRM_SHIFT) > - > -/* Vector Fixed-Point saturation flag */ > -#define FSR_VXSAT_SHIFT 8 > -#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) > - > /* Control and Status Registers */ > > /* User Trap Setup */
On Tue, Jan 30, 2024 at 9:10 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote: > > vxrm and vxsat have been moved into a special register vcsr since > RVV v1.0. So remove them from FCSR for vector 1.0. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu_bits.h | 8 -------- > 1 file changed, 8 deletions(-) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index ebd7917d49..e116f6c252 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -32,14 +32,6 @@ > #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) > #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) > > -/* Vector Fixed-Point round model */ > -#define FSR_VXRM_SHIFT 9 > -#define FSR_VXRM (0x3 << FSR_VXRM_SHIFT) > - > -/* Vector Fixed-Point saturation flag */ > -#define FSR_VXSAT_SHIFT 8 > -#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) > - > /* Control and Status Registers */ > > /* User Trap Setup */ > -- > 2.25.1 > >
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ebd7917d49..e116f6c252 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -32,14 +32,6 @@ #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) -/* Vector Fixed-Point round model */ -#define FSR_VXRM_SHIFT 9 -#define FSR_VXRM (0x3 << FSR_VXRM_SHIFT) - -/* Vector Fixed-Point saturation flag */ -#define FSR_VXSAT_SHIFT 8 -#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) - /* Control and Status Registers */ /* User Trap Setup */
vxrm and vxsat have been moved into a special register vcsr since RVV v1.0. So remove them from FCSR for vector 1.0. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> --- target/riscv/cpu_bits.h | 8 -------- 1 file changed, 8 deletions(-)