diff mbox series

[1/1] arm64: dts: imx8qxp: add GPU nodes

Message ID 20231218142312.3175828-1-alexander.stein@ew.tq-group.com (mailing list archive)
State New, archived
Headers show
Series [1/1] arm64: dts: imx8qxp: add GPU nodes | expand

Commit Message

Alexander Stein Dec. 18, 2023, 2:23 p.m. UTC 
Add the DT node for the GPU core found on the i.MX8QXP.

etnaviv-gpu 53100000.gpu: model: GC7000, revision: 6214
[drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
Based on downstream commit [1]. I am not aware if additional
modifications are necessary in etnaviv driver though. The revision
number is slightly different to the one from imx8mp:
etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6204

[1] https://github.com/Freescale/linux-fslc/commit/d0964b3f9afd8a75aca73921fdb0c128cc46c4fe

 .../boot/dts/freescale/imx8-ss-gpu0.dtsi      | 27 +++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi    |  1 +
 2 files changed, 28 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi

Comments

Frank Li Jan. 29, 2024, 5:11 p.m. UTC | #1 
On Mon, Dec 18, 2023 at 03:23:12PM +0100, Alexander Stein wrote:
> Add the DT node for the GPU core found on the i.MX8QXP.
> 
> etnaviv-gpu 53100000.gpu: model: GC7000, revision: 6214
> [drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0
> 
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
> Based on downstream commit [1]. I am not aware if additional
> modifications are necessary in etnaviv driver though. The revision
> number is slightly different to the one from imx8mp:
> etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6204
> 
> [1] https://github.com/Freescale/linux-fslc/commit/d0964b3f9afd8a75aca73921fdb0c128cc46c4fe
> 
>  .../boot/dts/freescale/imx8-ss-gpu0.dtsi      | 27 +++++++++++++++++++
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi    |  1 +
>  2 files changed, 28 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi
> new file mode 100644
> index 000000000000..9b8a44aa63d6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + *	Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +#include <dt-bindings/firmware/imx/rsrc.h>
> +
> +gpu0_subsys: bus@53000000 {
> +	compatible = "simple-bus";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	ranges = <0x53000000 0x0 0x53000000 0x1000000>;
> +
> +	gpu_3d0: gpu@53100000 {
> +		compatible = "vivante,gc";
> +		reg = <0x53100000 0x40000>;
> +		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
> +			 <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
> +		clock-names = "core", "shader";
> +		assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
> +				  <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
> +		assigned-clock-rates = <700000000>, <850000000>;
> +		power-domains = <&pd IMX_SC_R_GPU_0_PID0>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index fdbb4242b157..10e16d84c0c3 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -317,6 +317,7 @@ map0 {
>  	/* sorted in register address */
>  	#include "imx8-ss-img.dtsi"
>  	#include "imx8-ss-vpu.dtsi"
> +	#include "imx8-ss-gpu0.dtsi"
>  	#include "imx8-ss-adma.dtsi"
>  	#include "imx8-ss-conn.dtsi"
>  	#include "imx8-ss-ddr.dtsi"
> -- 
> 2.34.1
>
Shawn Guo Feb. 1, 2024, 10:09 a.m. UTC | #2 
On Mon, Dec 18, 2023 at 03:23:12PM +0100, Alexander Stein wrote:
> Add the DT node for the GPU core found on the i.MX8QXP.
> 
> etnaviv-gpu 53100000.gpu: model: GC7000, revision: 6214
> [drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0
> 
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Applied, thanks!
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi
new file mode 100644
index 000000000000..9b8a44aa63d6
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi
@@ -0,0 +1,27 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *	Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+gpu0_subsys: bus@53000000 {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x53000000 0x0 0x53000000 0x1000000>;
+
+	gpu_3d0: gpu@53100000 {
+		compatible = "vivante,gc";
+		reg = <0x53100000 0x40000>;
+		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
+			 <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
+		clock-names = "core", "shader";
+		assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
+				  <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
+		assigned-clock-rates = <700000000>, <850000000>;
+		power-domains = <&pd IMX_SC_R_GPU_0_PID0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index fdbb4242b157..10e16d84c0c3 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -317,6 +317,7 @@  map0 {
 	/* sorted in register address */
 	#include "imx8-ss-img.dtsi"
 	#include "imx8-ss-vpu.dtsi"
+	#include "imx8-ss-gpu0.dtsi"
 	#include "imx8-ss-adma.dtsi"
 	#include "imx8-ss-conn.dtsi"
 	#include "imx8-ss-ddr.dtsi"