| Message ID | 702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/2] dt-bindings: phy: mediatek,xfi-tphy: add new bindings | expand |
On 01/02/2024 22:52, Daniel Golle wrote: > Add bindings for the MediaTek XFI T-PHY Ethernet SerDes PHY found in the > MediaTek MT7988 SoC which can operate at various interfaces modes: > > via USXGMII PCS: > * USXGMII > * 10GBase-R > * 5GBase-R > > via LynxI SGMII PCS: > * 2500Base-X > * 1000Base-X > * Cisco SGMII (MAC side) > > Signed-off-by: Daniel Golle <daniel@makrotopia.org> > --- > .../bindings/phy/mediatek,xfi-tphy.yaml | 80 +++++++++++++++++++ > 1 file changed, 80 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > new file mode 100644 > index 0000000000000..e897118dcf7e6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > @@ -0,0 +1,80 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,xfi-tphy.yaml# Please use compatible as filename. Your binding says only one is possible (const, not enum), so there is no reasoning for different filename. > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek XFI T-PHY > + > +maintainers: > + - Daniel Golle <daniel@makrotopia.org> > + > +description: > + The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes > + used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in > + MediaTek's 10G-capabale SoCs. > + > +properties: > + $nodename: > + pattern: "^phy@[0-9a-f]+$" No need for nodename in individual bindings file. > + > + compatible: > + const: mediatek,mt7988-xfi-tphy > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: XFI PHY clock > + - description: XFI register clock > + > + clock-names: > + items: > + - const: xfipll > + - const: topxtal > + > + resets: > + items: > + - description: PEXTP reset > + > + mediatek,usxgmii-performance-errata: > + $ref: /schemas/types.yaml#/definitions/flag > + description: > + One instance of the T-PHY on MT7988 suffers from a performance > + problem in 10GBase-R mode which needs a work-around in the driver. Can you explain what is this issue and errata about (except performance)? > + The work-around is enabled using this flag. > + > + "#phy-cells": > + const: 0 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - resets > + - "#phy-cells" > + > +additionalProperties: false Best regards, Krzysztof
On Thu, Feb 01, 2024 at 09:52:20PM +0000, Daniel Golle wrote: > Add bindings for the MediaTek XFI T-PHY Ethernet SerDes PHY found in the > MediaTek MT7988 SoC which can operate at various interfaces modes: This is v4 unless I'm confused[1]. Where's the revision history? Rob [1] https://lore.kernel.org/all/b875f693f6d4367a610a12ef324584f3bf3a1c1c.1702352117.git.daniel@makrotopia.org/ > > via USXGMII PCS: > * USXGMII > * 10GBase-R > * 5GBase-R > > via LynxI SGMII PCS: > * 2500Base-X > * 1000Base-X > * Cisco SGMII (MAC side) > > Signed-off-by: Daniel Golle <daniel@makrotopia.org> > --- > .../bindings/phy/mediatek,xfi-tphy.yaml | 80 +++++++++++++++++++ > 1 file changed, 80 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > new file mode 100644 > index 0000000000000..e897118dcf7e6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > @@ -0,0 +1,80 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,xfi-tphy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek XFI T-PHY > + > +maintainers: > + - Daniel Golle <daniel@makrotopia.org> > + > +description: > + The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes > + used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in > + MediaTek's 10G-capabale SoCs. > + > +properties: > + $nodename: > + pattern: "^phy@[0-9a-f]+$" > + > + compatible: > + const: mediatek,mt7988-xfi-tphy > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: XFI PHY clock > + - description: XFI register clock > + > + clock-names: > + items: > + - const: xfipll > + - const: topxtal > + > + resets: > + items: > + - description: PEXTP reset What is PEXTP?
On Fri, Feb 02, 2024 at 03:24:20PM -0600, Rob Herring wrote: > On Thu, Feb 01, 2024 at 09:52:20PM +0000, Daniel Golle wrote: > > Add bindings for the MediaTek XFI T-PHY Ethernet SerDes PHY found in the > > MediaTek MT7988 SoC which can operate at various interfaces modes: > > This is v4 unless I'm confused[1]. Where's the revision history? It's a new series only covering the XFI T-PHY driver. However, I should have written a cover letter referencing the previous series to netdev. Sorry for that and thank you for pointing it out. > > Rob > > [1] https://lore.kernel.org/all/b875f693f6d4367a610a12ef324584f3bf3a1c1c.1702352117.git.daniel@makrotopia.org/ > > > > > via USXGMII PCS: > > * USXGMII > > * 10GBase-R > > * 5GBase-R > > > > via LynxI SGMII PCS: > > * 2500Base-X > > * 1000Base-X > > * Cisco SGMII (MAC side) > > > > Signed-off-by: Daniel Golle <daniel@makrotopia.org> > > --- > > .../bindings/phy/mediatek,xfi-tphy.yaml | 80 +++++++++++++++++++ > > 1 file changed, 80 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > > > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > > new file mode 100644 > > index 0000000000000..e897118dcf7e6 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > > @@ -0,0 +1,80 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/mediatek,xfi-tphy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek XFI T-PHY > > + > > +maintainers: > > + - Daniel Golle <daniel@makrotopia.org> > > + > > +description: > > + The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes > > + used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in > > + MediaTek's 10G-capabale SoCs. > > + > > +properties: > > + $nodename: > > + pattern: "^phy@[0-9a-f]+$" > > + > > + compatible: > > + const: mediatek,mt7988-xfi-tphy > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: XFI PHY clock > > + - description: XFI register clock > > + > > + clock-names: > > + items: > > + - const: xfipll > > + - const: topxtal > > + > > + resets: > > + items: > > + - description: PEXTP reset > > What is PEXTP? >
On Fri, 2024-02-02 at 09:21 +0100, Krzysztof Kozlowski wrote: > > External email : Please do not click links or open attachments until > you have verified the sender or the content. > On 01/02/2024 22:52, Daniel Golle wrote: > > Add bindings for the MediaTek XFI T-PHY Ethernet SerDes PHY found > in the > > MediaTek MT7988 SoC which can operate at various interfaces modes: > > > > via USXGMII PCS: > > * USXGMII > > * 10GBase-R > > * 5GBase-R > > > > via LynxI SGMII PCS: > > * 2500Base-X > > * 1000Base-X > > * Cisco SGMII (MAC side) > > > > Signed-off-by: Daniel Golle <daniel@makrotopia.org> > > --- > > .../bindings/phy/mediatek,xfi-tphy.yaml | 80 > +++++++++++++++++++ > > 1 file changed, 80 insertions(+) > > create mode 100644 > Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > > > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,xfi- > tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xfi- > tphy.yaml > > new file mode 100644 > > index 0000000000000..e897118dcf7e6 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml > > @@ -0,0 +1,80 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/mediatek,xfi-tphy.yaml# > > Please use compatible as filename. Your binding says only one is > possible (const, not enum), so there is no reasoning for different > filename. > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek XFI T-PHY > > + > > +maintainers: > > + - Daniel Golle <daniel@makrotopia.org> > > + > > +description: > > + The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes > > + used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found > in > > + MediaTek's 10G-capabale SoCs. > > + > > +properties: > > + $nodename: > > + pattern: "^phy@[0-9a-f]+$" > > No need for nodename in individual bindings file. > > > + > > + compatible: > > + const: mediatek,mt7988-xfi-tphy Add a generic compatible "mediatek,xfi-tphy"? Other socs also use this phy but not upstream. > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: XFI PHY clock > > + - description: XFI register clock > > + > > + clock-names: > > + items: > > + - const: xfipll > > + - const: topxtal > > + > > + resets: > > + items: > > + - description: PEXTP reset > > + > > + mediatek,usxgmii-performance-errata: > > + $ref: /schemas/types.yaml#/definitions/flag > > + description: > > + One instance of the T-PHY on MT7988 suffers from a > performance > > + problem in 10GBase-R mode which needs a work-around in the > driver. > > Can you explain what is this issue and errata about (except > performance)? > > > + The work-around is enabled using this flag. > > + > > + "#phy-cells": > > + const: 0 > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - resets > > + - "#phy-cells" > > + > > +additionalProperties: false > > > Best regards, > Krzysztof >
On 04/02/2024 07:17, Chunfeng Yun (云春峰) wrote: > On Fri, 2024-02-02 at 09:21 +0100, Krzysztof Kozlowski wrote: >> >> External email : Please do not click links or open attachments until >> you have verified the sender or the content. >> On 01/02/2024 22:52, Daniel Golle wrote: >>> Add bindings for the MediaTek XFI T-PHY Ethernet SerDes PHY found >> in the >>> MediaTek MT7988 SoC which can operate at various interfaces modes: >>> >>> via USXGMII PCS: >>> * USXGMII >>> * 10GBase-R >>> * 5GBase-R >>> >>> via LynxI SGMII PCS: >>> * 2500Base-X >>> * 1000Base-X >>> * Cisco SGMII (MAC side) >>> >>> Signed-off-by: Daniel Golle <daniel@makrotopia.org> >>> --- >>> .../bindings/phy/mediatek,xfi-tphy.yaml | 80 >> +++++++++++++++++++ >>> 1 file changed, 80 insertions(+) >>> create mode 100644 >> Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/phy/mediatek,xfi- >> tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xfi- >> tphy.yaml >>> new file mode 100644 >>> index 0000000000000..e897118dcf7e6 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml >>> @@ -0,0 +1,80 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/phy/mediatek,xfi-tphy.yaml# >> >> Please use compatible as filename. Your binding says only one is >> possible (const, not enum), so there is no reasoning for different >> filename. >> >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: MediaTek XFI T-PHY >>> + >>> +maintainers: >>> + - Daniel Golle <daniel@makrotopia.org> >>> + >>> +description: >>> + The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes >>> + used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found >> in >>> + MediaTek's 10G-capabale SoCs. >>> + >>> +properties: >>> + $nodename: >>> + pattern: "^phy@[0-9a-f]+$" >> >> No need for nodename in individual bindings file. >> >>> + >>> + compatible: >>> + const: mediatek,mt7988-xfi-tphy > Add a generic compatible "mediatek,xfi-tphy"? > > Other socs also use this phy but not upstream. Are they here? No... They will use this one as fallback. Stop insisting on some generic fallbacks just because you do not like using other SoCs as fallbacks. You ignored other comments, so I understand you agree with them 100%. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml new file mode 100644 index 0000000000000..e897118dcf7e6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,xfi-tphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek XFI T-PHY + +maintainers: + - Daniel Golle <daniel@makrotopia.org> + +description: + The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes + used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in + MediaTek's 10G-capabale SoCs. + +properties: + $nodename: + pattern: "^phy@[0-9a-f]+$" + + compatible: + const: mediatek,mt7988-xfi-tphy + + reg: + maxItems: 1 + + clocks: + items: + - description: XFI PHY clock + - description: XFI register clock + + clock-names: + items: + - const: xfipll + - const: topxtal + + resets: + items: + - description: PEXTP reset + + mediatek,usxgmii-performance-errata: + $ref: /schemas/types.yaml#/definitions/flag + description: + One instance of the T-PHY on MT7988 suffers from a performance + problem in 10GBase-R mode which needs a work-around in the driver. + The work-around is enabled using this flag. + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mediatek,mt7988-clk.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy@11f20000 { + compatible = "mediatek,mt7988-xfi-tphy"; + reg = <0 0x11f20000 0 0x10000>; + clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, + <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; + clock-names = "xfipll", "topxtal"; + resets = <&watchdog 14>; + mediatek,usxgmii-performance-errata; + #phy-cells = <0>; + }; + }; + +...
Add bindings for the MediaTek XFI T-PHY Ethernet SerDes PHY found in the MediaTek MT7988 SoC which can operate at various interfaces modes: via USXGMII PCS: * USXGMII * 10GBase-R * 5GBase-R via LynxI SGMII PCS: * 2500Base-X * 1000Base-X * Cisco SGMII (MAC side) Signed-off-by: Daniel Golle <daniel@makrotopia.org> --- .../bindings/phy/mediatek,xfi-tphy.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml