| Message ID | 20240131102344.1671929-2-arun.r.murthy@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [PATCHv2,1/2] drm/display/dp: Check for MSTM_CAP before MSTM_CTRL write | expand |
On Wed, 31 Jan 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote: > With a value of '0' read from MSTM_CAP register MST to be enabled. > DP2.1 SCR updates the spec for 128/132b DP capable supporting only one > stream and not supporting single stream sideband MSG. > The underlying protocol will be MST to enable use of MTP. > > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 9ff0cbd9c0df..05722f10cdd7 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4037,9 +4037,15 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) > > if (!intel_dp_mst_source_support(intel_dp)) > return; > - > - intel_dp->is_mst = sink_can_mst && > - i915->display.params.enable_dp_mst; > + /* > + * Even if dpcd reg MSTM_CAP is 0, if the sink supports UHBR rates then > + * DP2.1 can be enabled with underlying protocol using MST for MTP > + * TODO: Need to accommodate MSTM_CAP bit[0]=0, bit[1]=1 condition, i.e > + * one stream with single stream sideband msg. > + */ > + intel_dp->is_mst = (sink_can_mst || (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & > + DP_CAP_ANSI_128B132B)) && > + i915->display.params.enable_dp_mst; Based on testing with the specific display in question, it looks like this works because the display, while having DP_MSTM_CAP == 0, does actually support sideband messaging. Which is unexpected. This means a display that has DP_MSTM_CAP == 0 that actually does not support sideband messaging, which is expected, will get a black screen with this patch. This was the conclusion when I discussed this with Ville and Imre. Related to this, I've posted a series to enable MST mode for 128b/132b displays that support single-stream with sideband messaging [1]. It obviously does not directly help here, as that requires DP_MSTM_CAP == 2. It might be possible to quirk the one display to use that. Maybe. The alternative is actually implementing 128b/132b single-stream w/o sideband messaging using our regular SST paths. BR, Jani. [1] https://patchwork.freedesktop.org/series/129468/ > > drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, > intel_dp->is_mst);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9ff0cbd9c0df..05722f10cdd7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4037,9 +4037,15 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) if (!intel_dp_mst_source_support(intel_dp)) return; - - intel_dp->is_mst = sink_can_mst && - i915->display.params.enable_dp_mst; + /* + * Even if dpcd reg MSTM_CAP is 0, if the sink supports UHBR rates then + * DP2.1 can be enabled with underlying protocol using MST for MTP + * TODO: Need to accommodate MSTM_CAP bit[0]=0, bit[1]=1 condition, i.e + * one stream with single stream sideband msg. + */ + intel_dp->is_mst = (sink_can_mst || (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & + DP_CAP_ANSI_128B132B)) && + i915->display.params.enable_dp_mst; drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
With a value of '0' read from MSTM_CAP register MST to be enabled. DP2.1 SCR updates the spec for 128/132b DP capable supporting only one stream and not supporting single stream sideband MSG. The underlying protocol will be MST to enable use of MTP. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)