[5.10.y-cip,00/48] Add support for Renesas RZ/Five RISC-V SoC

Message ID	20240205124135.14779-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
Headers	show Return-Path: <prabhakar.mahadev-lad.rj@bp.renesas.com> ip: 210.160.252.172, mailfrom: prabhakar.mahadev-lad.rj@bp.renesas.com) From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Biju Das <biju.das.jz@bp.renesas.com> Subject: [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC Date: Mon, 5 Feb 2024 12:40:47 +0000 Message-Id: <20240205124135.14779-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add support for Renesas RZ/Five RISC-V SoC \| expand [5.10.y-cip,00/48] Add support for Renesas RZ/Five RISC-V SoC [5.10.y-cip,01/48] ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and interrupt-names propert… [5.10.y-cip,02/48] ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels [5.10.y-cip,03/48] arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels [5.10.y-cip,04/48] arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels [5.10.y-cip,05/48] arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to board DTS [5.10.y-cip,06/48] arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS [5.10.y-cip,07/48] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify … [5.10.y-cip,08/48] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels [5.10.y-cip,09/48] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts [5.10.y-cip,10/48] cacheinfo: clear cache_leaves(cpu) in free_cache_attributes() [5.10.y-cip,11/48] riscv: Kconfig: Enable cpufreq kconfig menu [5.10.y-cip,12/48] dma-direct: add support for dma_coherent_default_memory [5.10.y-cip,13/48] dma-mapping: allow using the global coherent pool for !ARM [5.10.y-cip,14/48] dma-mapping: simplify dma_init_coherent_memory [5.10.y-cip,15/48] dma-mapping: add a dma_init_global_coherent helper [5.10.y-cip,16/48] dma-mapping: make the global coherent pool conditional [5.10.y-cip,17/48] of: also handle dma-noncoherent in of_dma_is_coherent() [5.10.y-cip,18/48] of/irq: Use interrupts-extended to find parent [5.10.y-cip,19/48] irqchip/sifive-plic: Improve naming scheme for per context offsets [5.10.y-cip,20/48] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode [5.10.y-cip,21/48] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC [5.10.y-cip,22/48] irqchip/sifive-plic: Make better use of the effective affinity mask [5.10.y-cip,23/48] irqchip/sifive-plic: Separate the enable and mask operations [5.10.y-cip,24/48] clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC [5.10.y-cip,25/48] clocksource/drivers/riscv: Increase the clock source rating [5.10.y-cip,26/48] clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback [5.10.y-cip,27/48] mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option dependant on ARCH_… [5.10.y-cip,28/48] dt-bindings: riscv: Sort the CPU core list alphabetically [5.10.y-cip,29/48] dt-bindings: riscv: Add Andes AX45MP core to the list [5.10.y-cip,30/48] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Defin… [5.10.y-cip,31/48] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 … [5.10.y-cip,32/48] soc: renesas: Identify RZ/Five SoC [5.10.y-cip,33/48] clk: renesas: r9a07g043: Add support for RZ/Five SoC [5.10.y-cip,34/48] cache: Add L2 cache management for Andes AX45MP RISC-V core [5.10.y-cip,35/48] cache: ax45mp_cache: Add non coherent support [5.10.y-cip,36/48] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC [5.10.y-cip,37/48] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option [5.10.y-cip,38/48] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC [5.10.y-cip,39/48] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK [5.10.y-cip,40/48] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/T… [5.10.y-cip,41/48] riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C [5.10.y-cip,42/48] riscv: dts: renesas: rzfive-smarc-som: Enable WDT [5.10.y-cip,43/48] riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes [5.10.y-cip,44/48] riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for ETH{0,1} [5.10.y-cip,45/48] riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node [5.10.y-cip,46/48] riscv: dts: renesas: r9a07g043f: Add L2 cache node [5.10.y-cip,47/48] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property [5.10.y-cip,48/48] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disab…

Message ID

20240205124135.14779-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)

Headers

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
To: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Pavel Machek <pavel@denx.de>
Cc: Biju Das <biju.das.jz@bp.renesas.com>
Subject: [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC
Date: Mon,  5 Feb 2024 12:40:47 +0000
Message-Id: <20240205124135.14779-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

Series

Add support for Renesas RZ/Five RISC-V SoC | expand

Message

Lad Prabhakar Feb. 5, 2024, 12:40 p.m. UTC

Hi All,

This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
support for this SoC has already been added to 6.1-cip kernel.

RFC->v1
* Patch #35 updated according uptstream for easier maitainance.
  Rest of the patches have been unchanged.
* Merged RFC series [0] and preporatory series [1].
* Previous test run results can be found at [2].
* RISC-V Renesas defconfig file can be found at [3].

[0] https://patchwork.kernel.org/project/cip-dev/cover/20240130203346.94488-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[1] https://patchwork.kernel.org/project/cip-dev/cover/20240130161555.85042-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[2] https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1160504705
[3] https://gitlab.com/cip-project/cip-kernel/cip-kernel-config/-/blob/rzfive-5.10-cip/5.10.y-cip/riscv/renesas_defconfig?ref_type=heads

Cheers,
Prabhakar

Christoph Hellwig (5):
  dma-direct: add support for dma_coherent_default_memory
  dma-mapping: allow using the global coherent pool for !ARM
  dma-mapping: simplify dma_init_coherent_memory
  dma-mapping: add a dma_init_global_coherent helper
  dma-mapping: make the global coherent pool conditional

Conor Dooley (1):
  riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy
    node

Heiko Stuebner (1):
  of: also handle dma-noncoherent in of_dma_is_coherent()

Lad Prabhakar (34):
  ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and
    interrupt-names properties
  ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels
  arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels
  arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels
  arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to
    board DTS
  arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS
  arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro
    to specify interrupt property
  arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels
  arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
  riscv: Kconfig: Enable cpufreq kconfig menu
  irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
  clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC
  clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback
  mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option
    dependant on ARCH_RENESAS
  dt-bindings: riscv: Sort the CPU core list alphabetically
  dt-bindings: riscv: Add Andes AX45MP core to the list
  dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and
    Reset Definitions
  dt-bindings: cache: andestech,ax45mp-cache: Add DT binding
    documentation for L2 cache controller
  soc: renesas: Identify RZ/Five SoC
  clk: renesas: r9a07g043: Add support for RZ/Five SoC
  cache: Add L2 cache management for Andes AX45MP RISC-V core
  cache: ax45mp_cache: Add non coherent support
  soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
  riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
  riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
  riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
  riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable
    ADC/OPP/Thermal Zones/TSU
  riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
  riscv: dts: renesas: rzfive-smarc-som: Enable WDT
  riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes
  riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for
    ETH{0,1}
  riscv: dts: renesas: r9a07g043f: Add L2 cache node
  riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property
  riscv: dts: renesas: rzfive-smarc: Enable the blocks which were
    explicitly disabled

Niklas Cassel (2):
  irqchip/sifive-plic: Improve naming scheme for per context offsets
  irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode

Samuel Holland (4):
  of/irq: Use interrupts-extended to find parent
  irqchip/sifive-plic: Make better use of the effective affinity mask
  irqchip/sifive-plic: Separate the enable and mask operations
  clocksource/drivers/riscv: Increase the clock source rating

Xiongfeng Wang (1):
  cacheinfo: clear cache_leaves(cpu) in free_cache_attributes()

 .../cache/andestech,ax45mp-cache.yaml         |  81 ++++
 .../devicetree/bindings/riscv/cpus.yaml       |   7 +-
 .../bindings/sound/renesas,rz-ssi.yaml        |  21 +-
 MAINTAINERS                                   |   7 +
 arch/arm64/boot/dts/renesas/r9a07g043.dtsi    | 350 ++++++++----------
 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi   |  72 ++++
 .../boot/dts/renesas/r9a07g043u11-smarc.dts   |  17 +-
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi    |  19 +-
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi    |  19 +-
 arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi |  14 -
 arch/riscv/Kconfig                            |   3 +-
 arch/riscv/Kconfig.socs                       |   5 +
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/renesas/Makefile          |   2 +
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi   |  72 ++++
 .../boot/dts/renesas/r9a07g043f01-smarc.dts   |  27 ++
 .../boot/dts/renesas/rzfive-smarc-som.dtsi    |  24 ++
 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi |   8 +
 arch/riscv/kernel/time.c                      |   9 -
 drivers/Kconfig                               |   2 +
 drivers/Makefile                              |   1 +
 drivers/base/cacheinfo.c                      |   1 +
 drivers/cache/Kconfig                         |  12 +
 drivers/cache/Makefile                        |   3 +
 drivers/cache/ax45mp_cache.c                  | 239 ++++++++++++
 drivers/clk/renesas/r9a07g043-cpg.c           |  32 ++
 drivers/clocksource/renesas-ostm.c            |   2 +-
 drivers/clocksource/timer-riscv.c             |   7 +-
 drivers/irqchip/Kconfig                       |   1 +
 drivers/irqchip/irq-sifive-plic.c             | 178 ++++++---
 drivers/mmc/host/Kconfig                      |   4 +-
 drivers/of/address.c                          |  17 +-
 drivers/of/irq.c                              |  13 +-
 drivers/soc/renesas/Kconfig                   |  12 +
 drivers/soc/renesas/renesas-soc.c             |  13 +
 include/dt-bindings/clock/r9a07g043-cpg.h     |  20 +
 include/linux/dma-map-ops.h                   |  18 +-
 kernel/dma/Kconfig                            |   4 +
 kernel/dma/coherent.c                         | 161 ++++----
 kernel/dma/direct.c                           |  17 +
 sound/soc/sh/rz-ssi.c                         |  63 +++-
 41 files changed, 1143 insertions(+), 435 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
 create mode 100644 arch/riscv/boot/dts/renesas/Makefile
 create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
 create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
 create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
 create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/ax45mp_cache.c

Comments

Pavel Machek Feb. 5, 2024, 7:33 p.m. UTC | #1

Hi!

> This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
> support for this SoC has already been added to 6.1-cip kernel.
> 
> RFC->v1
> * Patch #35 updated according uptstream for easier maitainance.
>   Rest of the patches have been unchanged.
> * Merged RFC series [0] and preporatory series [1].
> * Previous test run results can be found at [2].
> * RISC-V Renesas defconfig file can be found at [3].

Thanks for patches. AFAICT 1..4 are already applied to the 5.10 tree,
so we won't duplicate those.

I only have minor comment to one of the patches, that should not
prevent merge. I can apply the series if there are no other comments.

I rely on you for testing. I'd like to see qemu-risv enabled for 5.10
and 6.1, so that we have more than once architecture.

Best regards,
								Pavel

Nobuhiro Iwamatsu Feb. 6, 2024, 8:20 a.m. UTC | #2

Hi all,

> -----Original Message-----
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Sent: Monday, February 5, 2024 9:41 PM
> To: cip-dev@lists.cip-project.org; iwamatsu nobuhiro(岩松 信洋 ○ＤＩＴＣ□
> ＤＩＴ○ＯＳＴ) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>
> Subject: [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V
> SoC
> 
> Hi All,
> 
> This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
> support for this SoC has already been added to 6.1-cip kernel.
> 
> RFC->v1
> * Patch #35 updated according uptstream for easier maitainance.
>   Rest of the patches have been unchanged.
> * Merged RFC series [0] and preporatory series [1].
> * Previous test run results can be found at [2].
> * RISC-V Renesas defconfig file can be found at [3].
> 
> [0]
> https://patchwork.kernel.org/project/cip-dev/cover/20240130203346.94488-1
> -prabhakar.mahadev-lad.rj@bp.renesas.com/
> [1]
> https://patchwork.kernel.org/project/cip-dev/cover/20240130161555.85042-1
> -prabhakar.mahadev-lad.rj@bp.renesas.com/
> [2]
> https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/1160504705
> [3]
> https://gitlab.com/cip-project/cip-kernel/cip-kernel-config/-/blob/rzfive-5.1
> 0-cip/5.10.y-cip/riscv/renesas_defconfig?ref_type=heads
> 
> Cheers,
> Prabhakar
> 
> Christoph Hellwig (5):
>   dma-direct: add support for dma_coherent_default_memory
>   dma-mapping: allow using the global coherent pool for !ARM
>   dma-mapping: simplify dma_init_coherent_memory
>   dma-mapping: add a dma_init_global_coherent helper
>   dma-mapping: make the global coherent pool conditional
> 
> Conor Dooley (1):
>   riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy
>     node
> 
> Heiko Stuebner (1):
>   of: also handle dma-noncoherent in of_dma_is_coherent()
> 
> Lad Prabhakar (34):
>   ASoC: dt-bindings: renesas,rz-ssi: Update interrupts and
>     interrupt-names properties
>   ASoC: sh: rz-ssi: Update interrupt handling for half duplex channels
>   arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels
>   arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels
>   arm64: dts: renesas: rzg2ul-smarc: Move selecting PMOD_SCI0_EN to
>     board DTS
>   arm64: dts: renesas: rzg2ul-smarc: Include SoM DTSI into board DTS
>   arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro
>     to specify interrupt property
>   arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels
>   arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
>   riscv: Kconfig: Enable cpufreq kconfig menu
>   irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
>   clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoC
>   clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback
>   mmc: host: Kconfig: Make MMC_SDHI_INTERNAL_DMAC config option
>     dependant on ARCH_RENESAS
>   dt-bindings: riscv: Sort the CPU core list alphabetically
>   dt-bindings: riscv: Add Andes AX45MP core to the list
>   dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and
>     Reset Definitions
>   dt-bindings: cache: andestech,ax45mp-cache: Add DT binding
>     documentation for L2 cache controller
>   soc: renesas: Identify RZ/Five SoC
>   clk: renesas: r9a07g043: Add support for RZ/Five SoC
>   cache: Add L2 cache management for Andes AX45MP RISC-V core
>   cache: ax45mp_cache: Add non coherent support
>   soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
>   riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
>   riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
>   riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
>   riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable
>     ADC/OPP/Thermal Zones/TSU
>   riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2C
>   riscv: dts: renesas: rzfive-smarc-som: Enable WDT
>   riscv: dts: renesas: rzfive-smarc-som: Enable OSTM nodes
>   riscv: dts: renesas: rzfive-smarc-som: Drop PHY interrupt support for
>     ETH{0,1}
>   riscv: dts: renesas: r9a07g043f: Add L2 cache node
>   riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property
>   riscv: dts: renesas: rzfive-smarc: Enable the blocks which were
>     explicitly disabled
> 
> Niklas Cassel (2):
>   irqchip/sifive-plic: Improve naming scheme for per context offsets
>   irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode
> 
> Samuel Holland (4):
>   of/irq: Use interrupts-extended to find parent
>   irqchip/sifive-plic: Make better use of the effective affinity mask
>   irqchip/sifive-plic: Separate the enable and mask operations
>   clocksource/drivers/riscv: Increase the clock source rating
> 
> Xiongfeng Wang (1):
>   cacheinfo: clear cache_leaves(cpu) in free_cache_attributes()
> 
>  .../cache/andestech,ax45mp-cache.yaml         |  81 ++++
>  .../devicetree/bindings/riscv/cpus.yaml       |   7 +-
>  .../bindings/sound/renesas,rz-ssi.yaml        |  21 +-
>  MAINTAINERS                                   |   7 +
>  arch/arm64/boot/dts/renesas/r9a07g043.dtsi    | 350
> ++++++++----------
>  arch/arm64/boot/dts/renesas/r9a07g043u.dtsi   |  72 ++++
>  .../boot/dts/renesas/r9a07g043u11-smarc.dts   |  17 +-
>  arch/arm64/boot/dts/renesas/r9a07g044.dtsi    |  19 +-
>  arch/arm64/boot/dts/renesas/r9a07g054.dtsi    |  19 +-
>  arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi |  14 -
>  arch/riscv/Kconfig                            |   3 +-
>  arch/riscv/Kconfig.socs                       |   5 +
>  arch/riscv/boot/dts/Makefile                  |   1 +
>  arch/riscv/boot/dts/renesas/Makefile          |   2 +
>  arch/riscv/boot/dts/renesas/r9a07g043f.dtsi   |  72 ++++
>  .../boot/dts/renesas/r9a07g043f01-smarc.dts   |  27 ++
>  .../boot/dts/renesas/rzfive-smarc-som.dtsi    |  24 ++
>  arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi |   8 +
>  arch/riscv/kernel/time.c                      |   9 -
>  drivers/Kconfig                               |   2 +
>  drivers/Makefile                              |   1 +
>  drivers/base/cacheinfo.c                      |   1 +
>  drivers/cache/Kconfig                         |  12 +
>  drivers/cache/Makefile                        |   3 +
>  drivers/cache/ax45mp_cache.c                  | 239 ++++++++++++
>  drivers/clk/renesas/r9a07g043-cpg.c           |  32 ++
>  drivers/clocksource/renesas-ostm.c            |   2 +-
>  drivers/clocksource/timer-riscv.c             |   7 +-
>  drivers/irqchip/Kconfig                       |   1 +
>  drivers/irqchip/irq-sifive-plic.c             | 178 ++++++---
>  drivers/mmc/host/Kconfig                      |   4 +-
>  drivers/of/address.c                          |  17 +-
>  drivers/of/irq.c                              |  13 +-
>  drivers/soc/renesas/Kconfig                   |  12 +
>  drivers/soc/renesas/renesas-soc.c             |  13 +
>  include/dt-bindings/clock/r9a07g043-cpg.h     |  20 +
>  include/linux/dma-map-ops.h                   |  18 +-
>  kernel/dma/Kconfig                            |   4 +
>  kernel/dma/coherent.c                         | 161 ++++----
>  kernel/dma/direct.c                           |  17 +
>  sound/soc/sh/rz-ssi.c                         |  63 +++-
>  41 files changed, 1143 insertions(+), 435 deletions(-)  create mode 100644
> Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
>  create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
>  create mode 100644 arch/riscv/boot/dts/renesas/Makefile
>  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
>  create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
>  create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
>  create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
>  create mode 100644 drivers/cache/Kconfig  create mode 100644
> drivers/cache/Makefile  create mode 100644 drivers/cache/ax45mp_cache.c

I reviewed this series, there was nothing to point out without from 1/48 to 4/48.
# from 1/48 to 4/48 are already applied to Linux-5.10.y-cip.
I can apply this series, if there are no other comment.

Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>

Best regards,
  Nobuhiro

Pavel Machek Feb. 6, 2024, 8:29 a.m. UTC | #3

Hi!

> This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
> support for this SoC has already been added to 6.1-cip kernel.
> 
> RFC->v1
> * Patch #35 updated according uptstream for easier maitainance.
>   Rest of the patches have been unchanged.
> * Merged RFC series [0] and preporatory series [1].
> * Previous test run results can be found at [2].
> * RISC-V Renesas defconfig file can be found at [3].

I tried to apply/test the series, and besides 1..4 being already
applied, these failed, too:

Can you double-check?

> Christoph Hellwig (5):
>   dma-direct: add support for dma_coherent_default_memory
>   dma-mapping: allow using the global coherent pool for !ARM
>   dma-mapping: simplify dma_init_coherent_memory
>   dma-mapping: add a dma_init_global_coherent helper
>   dma-mapping: make the global coherent pool conditional

Best regards,
								Pavel

Lad Prabhakar Feb. 6, 2024, 9:02 a.m. UTC | #4

Hi Pavel,

> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: Tuesday, February 6, 2024 8:29 AM
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [PATCH 5.10.y-cip 00/48] Add support for Renesas RZ/Five RISC-V SoC
> 
> Hi!
> 
> > This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
> > support for this SoC has already been added to 6.1-cip kernel.
> >
> > RFC->v1
> > * Patch #35 updated according uptstream for easier maitainance.
> >   Rest of the patches have been unchanged.
> > * Merged RFC series [0] and preporatory series [1].
> > * Previous test run results can be found at [2].
> > * RISC-V Renesas defconfig file can be found at [3].
> 
> I tried to apply/test the series, and besides 1..4 being already applied, these failed, too:
> 
> Can you double-check?
> 
Can you please point me to the pipeline.

Cheers,
Prabhakar

> > Christoph Hellwig (5):
> >   dma-direct: add support for dma_coherent_default_memory
> >   dma-mapping: allow using the global coherent pool for !ARM
> >   dma-mapping: simplify dma_init_coherent_memory
> >   dma-mapping: add a dma_init_global_coherent helper
> >   dma-mapping: make the global coherent pool conditional
> 
> Best regards,
> 								Pavel
> --
> DENX Software Engineering GmbH,        Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Pavel Machek Feb. 6, 2024, 9:08 a.m. UTC | #5

Hi!

> > > This patch series aims to add support for Renesas RZ/Five RISC-V SoC,
> > > support for this SoC has already been added to 6.1-cip kernel.
> > >
> > > RFC->v1
> > > * Patch #35 updated according uptstream for easier maitainance.
> > >   Rest of the patches have been unchanged.
> > > * Merged RFC series [0] and preporatory series [1].
> > > * Previous test run results can be found at [2].
> > > * RISC-V Renesas defconfig file can be found at [3].
> > 
> > I tried to apply/test the series, and besides 1..4 being already applied, these failed, too:
> > 
> > Can you double-check?
> > 
> Can you please point me to the pipeline.

git am failed for me, so I don't really have a pipeline. Do I need to
double-check? :-)

Best regards,
								Pavel