| Message ID | 20240207143509.2607428-1-animesh.manna@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/panelreplay: Panel replay workaround with VRR | expand |
On Wed, 2024-02-07 at 20:05 +0530, Animesh Manna wrote: > Panel Replay VSC SDP not getting sent when VRR is enabled > and W1 and W2 are 0. So Program Set Context Latency in > TRANS_SET_CONTEXT_LATENCY register to at least a value of 1. Do you have Bspec number. You could add it here. > > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 1b844cac4c58..c1ec78b5b6c5 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2618,8 +2618,16 @@ static void intel_set_transcoder_timings(const > struct intel_crtc_state *crtc_sta > * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank > start. > */ > if (DISPLAY_VER(dev_priv) >= 13) { > - intel_de_write(dev_priv, > TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), > - crtc_vblank_start - crtc_vdisplay); > + /* > + * WA: Program Set Context Latency in > TRANS_SET_CONTEXT_LATENCY register Do you have HSD number to add here? BR, Jouni Högander > + * to at least a value of 1 when Panel Replay is > enabled with VRR. > + */ > + if (crtc_state->vrr.enable && crtc_state- > >has_panel_replay && > + (crtc_vblank_start == crtc_vdisplay)) > + intel_de_write(dev_priv, > TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), 1); > + else > + intel_de_write(dev_priv, > TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), > + crtc_vblank_start - > crtc_vdisplay); > > /* > * VBLANK_START not used by hw, just clear it
On Wed, Feb 07, 2024 at 08:05:09PM +0530, Animesh Manna wrote: > Panel Replay VSC SDP not getting sent when VRR is enabled > and W1 and W2 are 0. So Program Set Context Latency in > TRANS_SET_CONTEXT_LATENCY register to at least a value of 1. > > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 1b844cac4c58..c1ec78b5b6c5 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2618,8 +2618,16 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta > * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. > */ > if (DISPLAY_VER(dev_priv) >= 13) { > - intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), > - crtc_vblank_start - crtc_vdisplay); > + /* > + * WA: Program Set Context Latency in TRANS_SET_CONTEXT_LATENCY register > + * to at least a value of 1 when Panel Replay is enabled with VRR. > + */ > + if (crtc_state->vrr.enable && crtc_state->has_panel_replay && > + (crtc_vblank_start == crtc_vdisplay)) > + intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), 1); Nak. This needs to match the actual timings we have stored in the mode. > + else > + intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), > + crtc_vblank_start - crtc_vdisplay); > > /* > * VBLANK_START not used by hw, just clear it > -- > 2.29.0
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1b844cac4c58..c1ec78b5b6c5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2618,8 +2618,16 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. */ if (DISPLAY_VER(dev_priv) >= 13) { - intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), - crtc_vblank_start - crtc_vdisplay); + /* + * WA: Program Set Context Latency in TRANS_SET_CONTEXT_LATENCY register + * to at least a value of 1 when Panel Replay is enabled with VRR. + */ + if (crtc_state->vrr.enable && crtc_state->has_panel_replay && + (crtc_vblank_start == crtc_vdisplay)) + intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), 1); + else + intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), + crtc_vblank_start - crtc_vdisplay); /* * VBLANK_START not used by hw, just clear it
Panel Replay VSC SDP not getting sent when VRR is enabled and W1 and W2 are 0. So Program Set Context Latency in TRANS_SET_CONTEXT_LATENCY register to at least a value of 1. Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)