| Message ID | 20240210015223.24670-16-quic_parellan@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for CDM over DP | expand |
On Sat, 10 Feb 2024 at 03:52, Paloma Arellano <quic_parellan@quicinc.com> wrote: > > DP controller can be setup to operate in either SDP update flush mode or > peripheral flush mode based on the DP controller hardware version. > > Starting in DP v1.2, the hardware documents require the use of > peripheral flush mode for SDP packets such as PPS OR VSC SDP packets. > > In-line with this guidance, lets program the DP controller to use > peripheral flush mode starting DP v1.2 > > Changes in v2: > - Use the original dp_catalog_hw_revision() function to > correctly check the DP HW version > > Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> > --- > drivers/gpu/drm/msm/dp/dp_catalog.c | 17 +++++++++++++++++ > drivers/gpu/drm/msm/dp/dp_catalog.h | 1 + > drivers/gpu/drm/msm/dp/dp_ctrl.c | 1 + > drivers/gpu/drm/msm/dp/dp_reg.h | 2 ++ > 4 files changed, 21 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c > index 0f28a4897b7b7..bc64dde5b7459 100644 > --- a/drivers/gpu/drm/msm/dp/dp_catalog.c > +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c > @@ -440,6 +440,23 @@ void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, > dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val); > } > > +void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog) > +{ > + u32 mainlink_ctrl, hw_revision; > + struct dp_catalog_private *catalog = container_of(dp_catalog, > + struct dp_catalog_private, dp_catalog); > + > + mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); > + > + hw_revision = dp_catalog_hw_revision(dp_catalog); > + if (hw_revision >= DP_HW_VERSION_1_2) > + mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; > + else > + mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; > + > + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); > +} > + > void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, > u32 rate, u32 stream_rate_khz, > bool fixed_nvid, bool is_ycbcr_420) > diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h > index 5b3a7ba40d55f..9e2b05544f610 100644 > --- a/drivers/gpu/drm/msm/dp/dp_catalog.h > +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h > @@ -98,6 +98,7 @@ void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config); > void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog); > void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable); > void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable); > +void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog); > void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb); > void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, > u32 stream_rate_khz, bool fixed_nvid, bool is_ycbcr_420); > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index beef86b1aaf81..f1e7b0a5ee5d1 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -170,6 +170,7 @@ static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) > > dp_catalog_ctrl_lane_mapping(ctrl->catalog); > dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); > + dp_catalog_setup_peripheral_flush(ctrl->catalog); > > dp_ctrl_config_ctrl(ctrl); > > diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h > index 2983756c125cd..6ac66532b47a4 100644 > --- a/drivers/gpu/drm/msm/dp/dp_reg.h > +++ b/drivers/gpu/drm/msm/dp/dp_reg.h > @@ -102,6 +102,8 @@ > #define DP_MAINLINK_CTRL_ENABLE (0x00000001) > #define DP_MAINLINK_CTRL_RESET (0x00000002) > #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) > +#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP (0x00800000) > +#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE (0x01800000) Just one bit here, please. > #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) > > #define REG_DP_STATE_CTRL (0x00000004) > -- > 2.39.2 >
On 2/10/2024 2:16 AM, Dmitry Baryshkov wrote: > On Sat, 10 Feb 2024 at 03:52, Paloma Arellano <quic_parellan@quicinc.com> wrote: >> >> DP controller can be setup to operate in either SDP update flush mode or >> peripheral flush mode based on the DP controller hardware version. >> >> Starting in DP v1.2, the hardware documents require the use of >> peripheral flush mode for SDP packets such as PPS OR VSC SDP packets. >> >> In-line with this guidance, lets program the DP controller to use >> peripheral flush mode starting DP v1.2 >> >> Changes in v2: >> - Use the original dp_catalog_hw_revision() function to >> correctly check the DP HW version >> >> Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> >> --- >> drivers/gpu/drm/msm/dp/dp_catalog.c | 17 +++++++++++++++++ >> drivers/gpu/drm/msm/dp/dp_catalog.h | 1 + >> drivers/gpu/drm/msm/dp/dp_ctrl.c | 1 + >> drivers/gpu/drm/msm/dp/dp_reg.h | 2 ++ >> 4 files changed, 21 insertions(+) >> <Snip> >> >> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h >> index 2983756c125cd..6ac66532b47a4 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_reg.h >> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h >> @@ -102,6 +102,8 @@ >> #define DP_MAINLINK_CTRL_ENABLE (0x00000001) >> #define DP_MAINLINK_CTRL_RESET (0x00000002) >> #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) >> +#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP (0x00800000) >> +#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE (0x01800000) > > Just one bit here, please. > hmm .... so the periph flush bits are 24:23 and we need a value of 3 to select peripheral flush which translates to 0x01800000. How do you suggest to break this up? >> #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) >> >> #define REG_DP_STATE_CTRL (0x00000004) >> -- >> 2.39.2 >> > >
On Sat, 10 Feb 2024 at 23:49, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote: > > > > On 2/10/2024 2:16 AM, Dmitry Baryshkov wrote: > > On Sat, 10 Feb 2024 at 03:52, Paloma Arellano <quic_parellan@quicinc.com> wrote: > >> > >> DP controller can be setup to operate in either SDP update flush mode or > >> peripheral flush mode based on the DP controller hardware version. > >> > >> Starting in DP v1.2, the hardware documents require the use of > >> peripheral flush mode for SDP packets such as PPS OR VSC SDP packets. > >> > >> In-line with this guidance, lets program the DP controller to use > >> peripheral flush mode starting DP v1.2 > >> > >> Changes in v2: > >> - Use the original dp_catalog_hw_revision() function to > >> correctly check the DP HW version > >> > >> Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> > >> --- > >> drivers/gpu/drm/msm/dp/dp_catalog.c | 17 +++++++++++++++++ > >> drivers/gpu/drm/msm/dp/dp_catalog.h | 1 + > >> drivers/gpu/drm/msm/dp/dp_ctrl.c | 1 + > >> drivers/gpu/drm/msm/dp/dp_reg.h | 2 ++ > >> 4 files changed, 21 insertions(+) > >> > > <Snip> > > >> > >> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h > >> index 2983756c125cd..6ac66532b47a4 100644 > >> --- a/drivers/gpu/drm/msm/dp/dp_reg.h > >> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h > >> @@ -102,6 +102,8 @@ > >> #define DP_MAINLINK_CTRL_ENABLE (0x00000001) > >> #define DP_MAINLINK_CTRL_RESET (0x00000002) > >> #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) > >> +#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP (0x00800000) > >> +#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE (0x01800000) > > > > Just one bit here, please. > > > > hmm .... so the periph flush bits are 24:23 and we need a value of 3 to > select peripheral flush which translates to 0x01800000. > > How do you suggest to break this up? Then FIELD_PREP(something_mask, 3). Otherwise it is too easy to consider it to be DP_MAINLINK_FLUSH_MODE_UPDATE_SDP | BIT(24) > > >> #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) > >> > >> #define REG_DP_STATE_CTRL (0x00000004) > >> -- > >> 2.39.2 > >> > > > >
On 2/10/2024 2:11 PM, Dmitry Baryshkov wrote: > On Sat, 10 Feb 2024 at 23:49, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote: >> >> >> >> On 2/10/2024 2:16 AM, Dmitry Baryshkov wrote: >>> On Sat, 10 Feb 2024 at 03:52, Paloma Arellano <quic_parellan@quicinc.com> wrote: >>>> >>>> DP controller can be setup to operate in either SDP update flush mode or >>>> peripheral flush mode based on the DP controller hardware version. >>>> >>>> Starting in DP v1.2, the hardware documents require the use of >>>> peripheral flush mode for SDP packets such as PPS OR VSC SDP packets. >>>> >>>> In-line with this guidance, lets program the DP controller to use >>>> peripheral flush mode starting DP v1.2 >>>> >>>> Changes in v2: >>>> - Use the original dp_catalog_hw_revision() function to >>>> correctly check the DP HW version >>>> >>>> Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> >>>> --- >>>> drivers/gpu/drm/msm/dp/dp_catalog.c | 17 +++++++++++++++++ >>>> drivers/gpu/drm/msm/dp/dp_catalog.h | 1 + >>>> drivers/gpu/drm/msm/dp/dp_ctrl.c | 1 + >>>> drivers/gpu/drm/msm/dp/dp_reg.h | 2 ++ >>>> 4 files changed, 21 insertions(+) >>>> >> >> <Snip> >> >>>> >>>> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h >>>> index 2983756c125cd..6ac66532b47a4 100644 >>>> --- a/drivers/gpu/drm/msm/dp/dp_reg.h >>>> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h >>>> @@ -102,6 +102,8 @@ >>>> #define DP_MAINLINK_CTRL_ENABLE (0x00000001) >>>> #define DP_MAINLINK_CTRL_RESET (0x00000002) >>>> #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) >>>> +#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP (0x00800000) >>>> +#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE (0x01800000) >>> >>> Just one bit here, please. >>> >> >> hmm .... so the periph flush bits are 24:23 and we need a value of 3 to >> select peripheral flush which translates to 0x01800000. >> >> How do you suggest to break this up? > > Then FIELD_PREP(something_mask, 3). Otherwise it is too easy to > consider it to be DP_MAINLINK_FLUSH_MODE_UPDATE_SDP | BIT(24) > Sure, FIELD_PREP() works. I was confused when you said one bit :) >> >>>> #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) >>>> >>>> #define REG_DP_STATE_CTRL (0x00000004) >>>> -- >>>> 2.39.2 >>>> >>> >>> > > >
On Sun, 11 Feb 2024 at 06:12, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote: > > > > On 2/10/2024 2:11 PM, Dmitry Baryshkov wrote: > > On Sat, 10 Feb 2024 at 23:49, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote: > >> > >> > >> > >> On 2/10/2024 2:16 AM, Dmitry Baryshkov wrote: > >>> On Sat, 10 Feb 2024 at 03:52, Paloma Arellano <quic_parellan@quicinc.com> wrote: > >>>> > >>>> DP controller can be setup to operate in either SDP update flush mode or > >>>> peripheral flush mode based on the DP controller hardware version. > >>>> > >>>> Starting in DP v1.2, the hardware documents require the use of > >>>> peripheral flush mode for SDP packets such as PPS OR VSC SDP packets. > >>>> > >>>> In-line with this guidance, lets program the DP controller to use > >>>> peripheral flush mode starting DP v1.2 > >>>> > >>>> Changes in v2: > >>>> - Use the original dp_catalog_hw_revision() function to > >>>> correctly check the DP HW version > >>>> > >>>> Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> > >>>> --- > >>>> drivers/gpu/drm/msm/dp/dp_catalog.c | 17 +++++++++++++++++ > >>>> drivers/gpu/drm/msm/dp/dp_catalog.h | 1 + > >>>> drivers/gpu/drm/msm/dp/dp_ctrl.c | 1 + > >>>> drivers/gpu/drm/msm/dp/dp_reg.h | 2 ++ > >>>> 4 files changed, 21 insertions(+) > >>>> > >> > >> <Snip> > >> > >>>> > >>>> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h > >>>> index 2983756c125cd..6ac66532b47a4 100644 > >>>> --- a/drivers/gpu/drm/msm/dp/dp_reg.h > >>>> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h > >>>> @@ -102,6 +102,8 @@ > >>>> #define DP_MAINLINK_CTRL_ENABLE (0x00000001) > >>>> #define DP_MAINLINK_CTRL_RESET (0x00000002) > >>>> #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) > >>>> +#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP (0x00800000) > >>>> +#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE (0x01800000) > >>> > >>> Just one bit here, please. > >>> > >> > >> hmm .... so the periph flush bits are 24:23 and we need a value of 3 to > >> select peripheral flush which translates to 0x01800000. > >> > >> How do you suggest to break this up? > > > > Then FIELD_PREP(something_mask, 3). Otherwise it is too easy to > > consider it to be DP_MAINLINK_FLUSH_MODE_UPDATE_SDP | BIT(24) > > > > Sure, FIELD_PREP() works. I was confused when you said one bit :) I was also confused, as I wrote, thus I thought that there are one-bit values in this reg. > > >> > >>>> #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) > >>>> > >>>> #define REG_DP_STATE_CTRL (0x00000004) > >>>> -- > >>>> 2.39.2 > >>>> > >>> > >>> > > > > > >
On 2/10/2024 10:15 PM, Dmitry Baryshkov wrote: > On Sun, 11 Feb 2024 at 06:12, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote: >> >> >> On 2/10/2024 2:11 PM, Dmitry Baryshkov wrote: >>> On Sat, 10 Feb 2024 at 23:49, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote: >>>> >>>> >>>> On 2/10/2024 2:16 AM, Dmitry Baryshkov wrote: >>>>> On Sat, 10 Feb 2024 at 03:52, Paloma Arellano <quic_parellan@quicinc.com> wrote: >>>>>> DP controller can be setup to operate in either SDP update flush mode or >>>>>> peripheral flush mode based on the DP controller hardware version. >>>>>> >>>>>> Starting in DP v1.2, the hardware documents require the use of >>>>>> peripheral flush mode for SDP packets such as PPS OR VSC SDP packets. >>>>>> >>>>>> In-line with this guidance, lets program the DP controller to use >>>>>> peripheral flush mode starting DP v1.2 >>>>>> >>>>>> Changes in v2: >>>>>> - Use the original dp_catalog_hw_revision() function to >>>>>> correctly check the DP HW version >>>>>> >>>>>> Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> >>>>>> --- >>>>>> drivers/gpu/drm/msm/dp/dp_catalog.c | 17 +++++++++++++++++ >>>>>> drivers/gpu/drm/msm/dp/dp_catalog.h | 1 + >>>>>> drivers/gpu/drm/msm/dp/dp_ctrl.c | 1 + >>>>>> drivers/gpu/drm/msm/dp/dp_reg.h | 2 ++ >>>>>> 4 files changed, 21 insertions(+) >>>>>> >>>> <Snip> >>>> >>>>>> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h >>>>>> index 2983756c125cd..6ac66532b47a4 100644 >>>>>> --- a/drivers/gpu/drm/msm/dp/dp_reg.h >>>>>> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h >>>>>> @@ -102,6 +102,8 @@ >>>>>> #define DP_MAINLINK_CTRL_ENABLE (0x00000001) >>>>>> #define DP_MAINLINK_CTRL_RESET (0x00000002) >>>>>> #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) >>>>>> +#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP (0x00800000) >>>>>> +#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE (0x01800000) >>>>> Just one bit here, please. >>>>> >>>> hmm .... so the periph flush bits are 24:23 and we need a value of 3 to >>>> select peripheral flush which translates to 0x01800000. >>>> >>>> How do you suggest to break this up? >>> Then FIELD_PREP(something_mask, 3). Otherwise it is too easy to >>> consider it to be DP_MAINLINK_FLUSH_MODE_UPDATE_SDP | BIT(24) >>> >> Sure, FIELD_PREP() works. I was confused when you said one bit :) > I was also confused, as I wrote, thus I thought that there are one-bit > values in this reg. Ack, will change -Paloma > >>>>>> #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) >>>>>> >>>>>> #define REG_DP_STATE_CTRL (0x00000004) >>>>>> -- >>>>>> 2.39.2 >>>>>> >>>>> >>> >>> > >
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 0f28a4897b7b7..bc64dde5b7459 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -440,6 +440,23 @@ void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val); } +void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog) +{ + u32 mainlink_ctrl, hw_revision; + struct dp_catalog_private *catalog = container_of(dp_catalog, + struct dp_catalog_private, dp_catalog); + + mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + + hw_revision = dp_catalog_hw_revision(dp_catalog); + if (hw_revision >= DP_HW_VERSION_1_2) + mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; + else + mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; + + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, u32 stream_rate_khz, bool fixed_nvid, bool is_ycbcr_420) diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index 5b3a7ba40d55f..9e2b05544f610 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -98,6 +98,7 @@ void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config); void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable); void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable); +void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb); void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, u32 stream_rate_khz, bool fixed_nvid, bool is_ycbcr_420); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index beef86b1aaf81..f1e7b0a5ee5d1 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -170,6 +170,7 @@ static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) dp_catalog_ctrl_lane_mapping(ctrl->catalog); dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); + dp_catalog_setup_peripheral_flush(ctrl->catalog); dp_ctrl_config_ctrl(ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 2983756c125cd..6ac66532b47a4 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -102,6 +102,8 @@ #define DP_MAINLINK_CTRL_ENABLE (0x00000001) #define DP_MAINLINK_CTRL_RESET (0x00000002) #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) +#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP (0x00800000) +#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE (0x01800000) #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) #define REG_DP_STATE_CTRL (0x00000004)
DP controller can be setup to operate in either SDP update flush mode or peripheral flush mode based on the DP controller hardware version. Starting in DP v1.2, the hardware documents require the use of peripheral flush mode for SDP packets such as PPS OR VSC SDP packets. In-line with this guidance, lets program the DP controller to use peripheral flush mode starting DP v1.2 Changes in v2: - Use the original dp_catalog_hw_revision() function to correctly check the DP HW version Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> --- drivers/gpu/drm/msm/dp/dp_catalog.c | 17 +++++++++++++++++ drivers/gpu/drm/msm/dp/dp_catalog.h | 1 + drivers/gpu/drm/msm/dp/dp_ctrl.c | 1 + drivers/gpu/drm/msm/dp/dp_reg.h | 2 ++ 4 files changed, 21 insertions(+)