| Message ID | 20240210-topic-1v-v1-3-fda0db38e29b@linaro.org (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Xperia 1 V support | expand |
On 12/02/2024 14:10, Konrad Dybcio wrote: > These peripherals are DMA-coherent on 8550. Mark them as such. > > Interestingly enough, the I2C master hubs are not. Yeah they are not DMA capable at all > > Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index b8f1c7f97e48..d696ec6c6850 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -812,6 +812,7 @@ gpi_dma2: dma-controller@800000 { > dma-channels = <12>; > dma-channel-mask = <0x3e>; > iommus = <&apps_smmu 0x436 0>; > + dma-coherent; > status = "disabled"; > }; > > @@ -823,6 +824,7 @@ qupv3_id_1: geniqup@8c0000 { > clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, > <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; > iommus = <&apps_smmu 0x423 0>; > + dma-coherent; > #address-cells = <2>; > #size-cells = <2>; > status = "disabled"; > @@ -1322,6 +1324,7 @@ gpi_dma1: dma-controller@a00000 { > dma-channels = <12>; > dma-channel-mask = <0x1e>; > iommus = <&apps_smmu 0xb6 0>; > + dma-coherent; > status = "disabled"; > }; > > @@ -1335,6 +1338,7 @@ qupv3_id_0: geniqup@ac0000 { > iommus = <&apps_smmu 0xa3 0>; > interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; > interconnect-names = "qup-core"; > + dma-coherent; > #address-cells = <2>; > #size-cells = <2>; > status = "disabled"; > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index b8f1c7f97e48..d696ec6c6850 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -812,6 +812,7 @@ gpi_dma2: dma-controller@800000 { dma-channels = <12>; dma-channel-mask = <0x3e>; iommus = <&apps_smmu 0x436 0>; + dma-coherent; status = "disabled"; }; @@ -823,6 +824,7 @@ qupv3_id_1: geniqup@8c0000 { clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; iommus = <&apps_smmu 0x423 0>; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; @@ -1322,6 +1324,7 @@ gpi_dma1: dma-controller@a00000 { dma-channels = <12>; dma-channel-mask = <0x1e>; iommus = <&apps_smmu 0xb6 0>; + dma-coherent; status = "disabled"; }; @@ -1335,6 +1338,7 @@ qupv3_id_0: geniqup@ac0000 { iommus = <&apps_smmu 0xa3 0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; interconnect-names = "qup-core"; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled";
These peripherals are DMA-coherent on 8550. Mark them as such. Interestingly enough, the I2C master hubs are not. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++ 1 file changed, 4 insertions(+)