| Message ID | 20240213145308.869874-1-alexghiti@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [RFC] target: riscv: Add Svvptc extension support | expand |
On Tue, Feb 13, 2024 at 03:53:08PM +0100, Alexandre Ghiti wrote: > The Svvptc extension describes a uarch that does not cache invalid TLB > entries: that's the case for qemu so there is nothing particular to > implement other than the introduction of this extension, which is done > here. > > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> > --- > > That's an RFC since the extension has not been ratified yet. Hi Alex, No need for the RFC tag. You can add not-yet-ratified extension support to QEMU as long as the CPU property is off by default (as you've done) and you add it to the riscv_cpu_experimental_exts[] array with an "x-" prefix on its property name. Thanks, drew > > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1b8d001d23..4beb5d0350 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -178,6 +178,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), > + ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_12_0, ext_svvptc), > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), > @@ -1467,6 +1468,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), > MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), > MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), > + MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, false), > > MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true), > MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 833bf58217..c973693b6e 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -77,6 +77,7 @@ struct RISCVCPUConfig { > bool ext_svinval; > bool ext_svnapot; > bool ext_svpbmt; > + bool ext_svvptc; > bool ext_zdinx; > bool ext_zaamo; > bool ext_zacas; > -- > 2.39.2 > >
Hi Andrew, Sorry for the very late reply, I was (and still am) off! On Tue, Feb 13, 2024 at 4:33 PM Andrew Jones <ajones@ventanamicro.com> wrote: > > On Tue, Feb 13, 2024 at 03:53:08PM +0100, Alexandre Ghiti wrote: > > The Svvptc extension describes a uarch that does not cache invalid TLB > > entries: that's the case for qemu so there is nothing particular to > > implement other than the introduction of this extension, which is done > > here. > > > > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> > > --- > > > > That's an RFC since the extension has not been ratified yet. > > Hi Alex, > > No need for the RFC tag. You can add not-yet-ratified extension support > to QEMU as long as the CPU property is off by default (as you've done) > and you add it to the riscv_cpu_experimental_exts[] array with an "x-" > prefix on its property name. > I'll do that next week then, Thanks, Alex > Thanks, > drew > > > > > target/riscv/cpu.c | 2 ++ > > target/riscv/cpu_cfg.h | 1 + > > 2 files changed, 3 insertions(+) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 1b8d001d23..4beb5d0350 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -178,6 +178,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), > > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), > > + ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_12_0, ext_svvptc), > > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > > ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), > > @@ -1467,6 +1468,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > > MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), > > MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), > > MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), > > + MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, false), > > > > MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true), > > MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true), > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > > index 833bf58217..c973693b6e 100644 > > --- a/target/riscv/cpu_cfg.h > > +++ b/target/riscv/cpu_cfg.h > > @@ -77,6 +77,7 @@ struct RISCVCPUConfig { > > bool ext_svinval; > > bool ext_svnapot; > > bool ext_svpbmt; > > + bool ext_svvptc; > > bool ext_zdinx; > > bool ext_zaamo; > > bool ext_zacas; > > -- > > 2.39.2 > > > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1b8d001d23..4beb5d0350 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -178,6 +178,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_12_0, ext_svvptc), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -1467,6 +1468,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), + MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, false), MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true), MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 833bf58217..c973693b6e 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -77,6 +77,7 @@ struct RISCVCPUConfig { bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; + bool ext_svvptc; bool ext_zdinx; bool ext_zaamo; bool ext_zacas;
The Svvptc extension describes a uarch that does not cache invalid TLB entries: that's the case for qemu so there is nothing particular to implement other than the introduction of this extension, which is done here. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> --- That's an RFC since the extension has not been ratified yet. target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+)