| Message ID | 20240206145721.2418893-2-msp@baylibre.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | viresh kumar |
| Headers | show |
| Series | arm64: am62: Use nvmem for chip information in opp table | expand |
On 06-02-24, 15:57, Markus Schneider-Pargmann wrote: > Add nvmem-cells to describe chip information like chipvariant and > chipspeed. If nvmem-cells are used, the syscon property is not necessary > anymore. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Acked-by: Andrew Davis <afd@ti.com> Rob, Can you please review / Ack this one ?
On 06/02/2024 15:57, Markus Schneider-Pargmann wrote: > Add nvmem-cells to describe chip information like chipvariant and > chipspeed. If nvmem-cells are used, the syscon property is not necessary > anymore. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Acked-by: Andrew Davis <afd@ti.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 15/02/2024 08:26, Viresh Kumar wrote: > On 06-02-24, 15:57, Markus Schneider-Pargmann wrote: >> Add nvmem-cells to describe chip information like chipvariant and >> chipspeed. If nvmem-cells are used, the syscon property is not necessary >> anymore. >> >> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> >> Acked-by: Andrew Davis <afd@ti.com> > > Rob, > > Can you please review / Ack this one ? Done now, although it is not aligned with DTS in this patchset, so this does not look tested... Best regards, Krzysztof
On 15-02-24, 09:25, Krzysztof Kozlowski wrote: > On 15/02/2024 08:26, Viresh Kumar wrote: > > On 06-02-24, 15:57, Markus Schneider-Pargmann wrote: > >> Add nvmem-cells to describe chip information like chipvariant and > >> chipspeed. If nvmem-cells are used, the syscon property is not necessary > >> anymore. > >> > >> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > >> Acked-by: Andrew Davis <afd@ti.com> > > > > Rob, > > > > Can you please review / Ack this one ? > > Done now, although it is not aligned with DTS in this patchset, so this > does not look tested... I will wait for them to be fixed then.
Hi, On Feb 06, 2024 at 15:57:19 +0100, Markus Schneider-Pargmann wrote: > Add nvmem-cells to describe chip information like chipvariant and > chipspeed. If nvmem-cells are used, the syscon property is not necessary > anymore. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Acked-by: Andrew Davis <afd@ti.com> > --- > .../bindings/opp/operating-points-v2-ti-cpu.yaml | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml > index 02d1d2c17129..b1881a0834fe 100644 > --- a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml > +++ b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml > @@ -34,6 +34,14 @@ properties: > points to syscon node representing the control module > register space of the SoC. > > + nvmem-cells: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + > + nvmem-cell-names: > + items: > + - const: chipvariant > + - const: chipspeed > + > opp-shared: true > > patternProperties: > @@ -55,7 +63,13 @@ patternProperties: > > required: > - compatible > - - syscon > + > +oneOf: > + - required: > + - syscon > + - required: > + - nvmem-cells > + - nvmem-cell-names Reviewed-by: Dhruva Gole <d-gole@ti.com>
On 15/02/2024 09:24, Krzysztof Kozlowski wrote: > On 06/02/2024 15:57, Markus Schneider-Pargmann wrote: >> Add nvmem-cells to describe chip information like chipvariant and >> chipspeed. If nvmem-cells are used, the syscon property is not necessary >> anymore. >> >> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> >> Acked-by: Andrew Davis <afd@ti.com> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> NAK And unreviewed. Please carry on: Nacked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> I found older discussion with Rob, who pointed out that one device cannot have entirely different programming models, so this patchset has the same errors. None of the previous issues were fixed here. Best regards, Krzysztof
On 06/02/2024 15:57, Markus Schneider-Pargmann wrote: > Add nvmem-cells to describe chip information like chipvariant and > chipspeed. If nvmem-cells are used, the syscon property is not necessary > anymore. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Acked-by: Andrew Davis <afd@ti.com> > --- > .../bindings/opp/operating-points-v2-ti-cpu.yaml | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml > index 02d1d2c17129..b1881a0834fe 100644 > --- a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml > +++ b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml > @@ -34,6 +34,14 @@ properties: > points to syscon node representing the control module > register space of the SoC. > > + nvmem-cells: > + $ref: /schemas/types.yaml#/definitions/phandle-array Why redefining the type? Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml index 02d1d2c17129..b1881a0834fe 100644 --- a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml @@ -34,6 +34,14 @@ properties: points to syscon node representing the control module register space of the SoC. + nvmem-cells: + $ref: /schemas/types.yaml#/definitions/phandle-array + + nvmem-cell-names: + items: + - const: chipvariant + - const: chipspeed + opp-shared: true patternProperties: @@ -55,7 +63,13 @@ patternProperties: required: - compatible - - syscon + +oneOf: + - required: + - syscon + - required: + - nvmem-cells + - nvmem-cell-names additionalProperties: false