| Message ID | 20240209183916.25860-1-will@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: errata: Don't enable workarounds for "rare" errata by default | expand |
On Fri, Feb 09, 2024 at 06:39:16PM +0000, Will Deacon wrote: > Arm classifies some of its CPU errata as "rare", indicating that the > hardware error is unlikely to occur in practice. Given that the cost of > errata workarounds can often be significant in terms of power and > performance, don't enable workarounds for "rare" errata by default and > update our documentation to reflect that. > > Cc: James Morse <james.morse@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Signed-off-by: Will Deacon <will@kernel.org> FWIW: Acked-by: Mark Rutland <mark.rutland@arm.com> Mark. > --- > Documentation/arch/arm64/silicon-errata.rst | 5 +++-- > arch/arm64/Kconfig | 25 +++++++++------------ > 2 files changed, 14 insertions(+), 16 deletions(-) > > diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst > index e8c2ce1f9df6..fa16b895c997 100644 > --- a/Documentation/arch/arm64/silicon-errata.rst > +++ b/Documentation/arch/arm64/silicon-errata.rst > @@ -35,8 +35,9 @@ can be triggered by Linux). > For software workarounds that may adversely impact systems unaffected by > the erratum in question, a Kconfig entry is added under "Kernel > Features" -> "ARM errata workarounds via the alternatives framework". > -These are enabled by default and patched in at runtime when an affected > -CPU is detected. For less-intrusive workarounds, a Kconfig option is not > +With the exception of workarounds for errata deemed "rare" by Arm, these > +are enabled by default and patched in at runtime when an affected CPU is > +detected. For less-intrusive workarounds, a Kconfig option is not > available and the code is structured (preferably with a comment) in such > a way that the erratum will not be hit. > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index aa7c1d435139..430fabf20f17 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -547,9 +547,8 @@ config ARM64_ERRATUM_832075 > If unsure, say Y. > > config ARM64_ERRATUM_834220 > - bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" > + bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" > depends on KVM > - default y > help > This option adds an alternative code sequence to work around ARM > erratum 834220 on Cortex-A57 parts up to r1p2. > @@ -565,7 +564,7 @@ config ARM64_ERRATUM_834220 > as it depends on the alternative framework, which will only patch > the kernel if an affected CPU is detected. > > - If unsure, say Y. > + If unsure, say N. > > config ARM64_ERRATUM_1742098 > bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" > @@ -692,8 +691,7 @@ config ARM64_WORKAROUND_REPEAT_TLBI > bool > > config ARM64_ERRATUM_2441007 > - bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" > - default y > + bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" > select ARM64_WORKAROUND_REPEAT_TLBI > help > This option adds a workaround for ARM Cortex-A55 erratum #2441007. > @@ -706,11 +704,10 @@ config ARM64_ERRATUM_2441007 > Work around this by adding the affected CPUs to the list that needs > TLB sequences to be done twice. > > - If unsure, say Y. > + If unsure, say N. > > config ARM64_ERRATUM_1286807 > - bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" > - default y > + bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" > select ARM64_WORKAROUND_REPEAT_TLBI > help > This option adds a workaround for ARM Cortex-A76 erratum 1286807. > @@ -724,6 +721,8 @@ config ARM64_ERRATUM_1286807 > invalidated has been observed by other observers. The > workaround repeats the TLBI+DSB operation. > > + If unsure, say N. > + > config ARM64_ERRATUM_1463225 > bool "Cortex-A76: Software Step might prevent interrupt recognition" > default y > @@ -743,8 +742,7 @@ config ARM64_ERRATUM_1463225 > If unsure, say Y. > > config ARM64_ERRATUM_1542419 > - bool "Neoverse-N1: workaround mis-ordering of instruction fetches" > - default y > + bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" > help > This option adds a workaround for ARM Neoverse-N1 erratum > 1542419. > @@ -756,7 +754,7 @@ config ARM64_ERRATUM_1542419 > Workaround the issue by hiding the DIC feature from EL0. This > forces user-space to perform cache maintenance. > > - If unsure, say Y. > + If unsure, say N. > > config ARM64_ERRATUM_1508412 > bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" > @@ -931,8 +929,7 @@ config ARM64_ERRATUM_2224489 > If unsure, say Y. > > config ARM64_ERRATUM_2441009 > - bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" > - default y > + bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" > select ARM64_WORKAROUND_REPEAT_TLBI > help > This option adds a workaround for ARM Cortex-A510 erratum #2441009. > @@ -945,7 +942,7 @@ config ARM64_ERRATUM_2441009 > Work around this by adding the affected CPUs to the list that needs > TLB sequences to be done twice. > > - If unsure, say Y. > + If unsure, say N. > > config ARM64_ERRATUM_2064142 > bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" > -- > 2.43.0.687.g38aa6559b0-goog > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >
On Fri, 09 Feb 2024 18:39:16 +0000, Will Deacon wrote: > Arm classifies some of its CPU errata as "rare", indicating that the > hardware error is unlikely to occur in practice. Given that the cost of > errata workarounds can often be significant in terms of power and > performance, don't enable workarounds for "rare" errata by default and > update our documentation to reflect that. > > > [...] Applied to arm64 (for-next/misc), thanks! [1/1] arm64: errata: Don't enable workarounds for "rare" errata by default https://git.kernel.org/arm64/c/8c10cc104b73
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index e8c2ce1f9df6..fa16b895c997 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -35,8 +35,9 @@ can be triggered by Linux). For software workarounds that may adversely impact systems unaffected by the erratum in question, a Kconfig entry is added under "Kernel Features" -> "ARM errata workarounds via the alternatives framework". -These are enabled by default and patched in at runtime when an affected -CPU is detected. For less-intrusive workarounds, a Kconfig option is not +With the exception of workarounds for errata deemed "rare" by Arm, these +are enabled by default and patched in at runtime when an affected CPU is +detected. For less-intrusive workarounds, a Kconfig option is not available and the code is structured (preferably with a comment) in such a way that the erratum will not be hit. diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index aa7c1d435139..430fabf20f17 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -547,9 +547,8 @@ config ARM64_ERRATUM_832075 If unsure, say Y. config ARM64_ERRATUM_834220 - bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" + bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" depends on KVM - default y help This option adds an alternative code sequence to work around ARM erratum 834220 on Cortex-A57 parts up to r1p2. @@ -565,7 +564,7 @@ config ARM64_ERRATUM_834220 as it depends on the alternative framework, which will only patch the kernel if an affected CPU is detected. - If unsure, say Y. + If unsure, say N. config ARM64_ERRATUM_1742098 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" @@ -692,8 +691,7 @@ config ARM64_WORKAROUND_REPEAT_TLBI bool config ARM64_ERRATUM_2441007 - bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" - default y + bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" select ARM64_WORKAROUND_REPEAT_TLBI help This option adds a workaround for ARM Cortex-A55 erratum #2441007. @@ -706,11 +704,10 @@ config ARM64_ERRATUM_2441007 Work around this by adding the affected CPUs to the list that needs TLB sequences to be done twice. - If unsure, say Y. + If unsure, say N. config ARM64_ERRATUM_1286807 - bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" - default y + bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" select ARM64_WORKAROUND_REPEAT_TLBI help This option adds a workaround for ARM Cortex-A76 erratum 1286807. @@ -724,6 +721,8 @@ config ARM64_ERRATUM_1286807 invalidated has been observed by other observers. The workaround repeats the TLBI+DSB operation. + If unsure, say N. + config ARM64_ERRATUM_1463225 bool "Cortex-A76: Software Step might prevent interrupt recognition" default y @@ -743,8 +742,7 @@ config ARM64_ERRATUM_1463225 If unsure, say Y. config ARM64_ERRATUM_1542419 - bool "Neoverse-N1: workaround mis-ordering of instruction fetches" - default y + bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" help This option adds a workaround for ARM Neoverse-N1 erratum 1542419. @@ -756,7 +754,7 @@ config ARM64_ERRATUM_1542419 Workaround the issue by hiding the DIC feature from EL0. This forces user-space to perform cache maintenance. - If unsure, say Y. + If unsure, say N. config ARM64_ERRATUM_1508412 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" @@ -931,8 +929,7 @@ config ARM64_ERRATUM_2224489 If unsure, say Y. config ARM64_ERRATUM_2441009 - bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" - default y + bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" select ARM64_WORKAROUND_REPEAT_TLBI help This option adds a workaround for ARM Cortex-A510 erratum #2441009. @@ -945,7 +942,7 @@ config ARM64_ERRATUM_2441009 Work around this by adding the affected CPUs to the list that needs TLB sequences to be done twice. - If unsure, say Y. + If unsure, say N. config ARM64_ERRATUM_2064142 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
Arm classifies some of its CPU errata as "rare", indicating that the hardware error is unlikely to occur in practice. Given that the cost of errata workarounds can often be significant in terms of power and performance, don't enable workarounds for "rare" errata by default and update our documentation to reflect that. Cc: James Morse <james.morse@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will@kernel.org> --- Documentation/arch/arm64/silicon-errata.rst | 5 +++-- arch/arm64/Kconfig | 25 +++++++++------------ 2 files changed, 14 insertions(+), 16 deletions(-)