| Message ID | 20240220100924.2761706-4-james.clark@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | kvm/coresight: Support exclude guest and exclude host | expand |
On Tue, Feb 20, 2024 at 10:09:13AM +0000, James Clark wrote: > Add separate definitions for ELx and EL2 as TRFCR_EL1 doesn't have CX. > This also mirrors the previous definition so no code change is required. This is also converting to automatic generation in the process. > +SysregFields TRFCR_EL2 > +Res0 63:7 > +UnsignedEnum 6:5 TS > + 0b0000 USE_TRFCR_EL1_TS > + 0b0001 VIRTUAL > + 0b0010 GUEST_PHYSICAL > + 0b0011 PHYSICAL > +EndEnum > +Res0 4 > +Field 3 CX > +Res0 2 > +Field 1 E2TRE > +Field 0 E0HTRE > +EndSysregFields This has exactly one user and I'd not expect more so why have a separate SysregFields? > +# TRFCR_EL1 doesn't have the CX bit so redefine it without CX instead of > +# using a shared definition between TRFCR_EL2 and TRFCR_EL1 This comment is reflecting the default state? > +Sysreg TRFCR_EL1 3 0 1 2 1 > +Fields TRFCR_ELx > +EndSysreg > + > +Sysreg TRFCR_EL2 3 4 1 2 1 > +Fields TRFCR_EL2 > +EndSysreg > + > +Sysreg TRFCR_EL12 3 5 1 2 1 > +Fields TRFCR_ELx > +EndSysreg These are generally sorted by encoding (simiarly to how sysreg.h was sorted historically).
On 20/02/2024 16:11, Mark Brown wrote: > On Tue, Feb 20, 2024 at 10:09:13AM +0000, James Clark wrote: >> Add separate definitions for ELx and EL2 as TRFCR_EL1 doesn't have CX. >> This also mirrors the previous definition so no code change is required. > > This is also converting to automatic generation in the process. > >> +SysregFields TRFCR_EL2 >> +Res0 63:7 >> +UnsignedEnum 6:5 TS >> + 0b0000 USE_TRFCR_EL1_TS >> + 0b0001 VIRTUAL >> + 0b0010 GUEST_PHYSICAL >> + 0b0011 PHYSICAL >> +EndEnum >> +Res0 4 >> +Field 3 CX >> +Res0 2 >> +Field 1 E2TRE >> +Field 0 E0HTRE >> +EndSysregFields > > This has exactly one user and I'd not expect more so why have a separate > SysregFields? > No reason, probably just a copy paste thing. I'll change it to a Sysreg. >> +# TRFCR_EL1 doesn't have the CX bit so redefine it without CX instead of >> +# using a shared definition between TRFCR_EL2 and TRFCR_EL1 > > This comment is reflecting the default state? > True, will remove. >> +Sysreg TRFCR_EL1 3 0 1 2 1 >> +Fields TRFCR_ELx >> +EndSysreg >> + >> +Sysreg TRFCR_EL2 3 4 1 2 1 >> +Fields TRFCR_EL2 >> +EndSysreg >> + >> +Sysreg TRFCR_EL12 3 5 1 2 1 >> +Fields TRFCR_ELx >> +EndSysreg > > These are generally sorted by encoding (simiarly to how sysreg.h was > sorted historically). Ah I didn't know that. Can I add a comment to the top of the file saying that it should be kept sorted?
On Wed, Feb 21, 2024 at 10:10:18AM +0000, James Clark wrote: > On 20/02/2024 16:11, Mark Brown wrote: > > These are generally sorted by encoding (simiarly to how sysreg.h was > > sorted historically). > Ah I didn't know that. Can I add a comment to the top of the file saying > that it should be kept sorted? Sure.
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9e8999592f3a..35890cf3c49f 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -280,8 +280,6 @@ #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) -#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) - #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) @@ -499,7 +497,6 @@ #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) -#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) @@ -961,15 +958,6 @@ /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) -#define TRFCR_ELx_TS_SHIFT 5 -#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_EL2_CX BIT(3) -#define TRFCR_ELx_ExTRE BIT(1) -#define TRFCR_ELx_E0TRE BIT(0) - /* GIC Hypervisor interface registers */ /* ICH_MISR_EL2 bit definitions */ #define ICH_MISR_EOI (1 << 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index fa3fe0856880..c4a6b77d2756 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2970,3 +2970,44 @@ Field 5 F Field 4 P Field 3:0 Align EndSysreg + +SysregFields TRFCR_EL2 +Res0 63:7 +UnsignedEnum 6:5 TS + 0b0000 USE_TRFCR_EL1_TS + 0b0001 VIRTUAL + 0b0010 GUEST_PHYSICAL + 0b0011 PHYSICAL +EndEnum +Res0 4 +Field 3 CX +Res0 2 +Field 1 E2TRE +Field 0 E0HTRE +EndSysregFields + +# TRFCR_EL1 doesn't have the CX bit so redefine it without CX instead of +# using a shared definition between TRFCR_EL2 and TRFCR_EL1 +SysregFields TRFCR_ELx +Res0 63:7 +UnsignedEnum 6:5 TS + 0b0001 VIRTUAL + 0b0010 GUEST_PHYSICAL + 0b0011 PHYSICAL +EndEnum +Res0 4:2 +Field 1 ExTRE +Field 0 E0TRE +EndSysregFields + +Sysreg TRFCR_EL1 3 0 1 2 1 +Fields TRFCR_ELx +EndSysreg + +Sysreg TRFCR_EL2 3 4 1 2 1 +Fields TRFCR_EL2 +EndSysreg + +Sysreg TRFCR_EL12 3 5 1 2 1 +Fields TRFCR_ELx +EndSysreg diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h index 9e8999592f3a..35890cf3c49f 100644 --- a/tools/arch/arm64/include/asm/sysreg.h +++ b/tools/arch/arm64/include/asm/sysreg.h @@ -280,8 +280,6 @@ #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) -#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) - #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) @@ -499,7 +497,6 @@ #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) -#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0) #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) @@ -961,15 +958,6 @@ /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) -#define TRFCR_ELx_TS_SHIFT 5 -#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_EL2_CX BIT(3) -#define TRFCR_ELx_ExTRE BIT(1) -#define TRFCR_ELx_E0TRE BIT(0) - /* GIC Hypervisor interface registers */ /* ICH_MISR_EL2 bit definitions */ #define ICH_MISR_EOI (1 << 0)
Add separate definitions for ELx and EL2 as TRFCR_EL1 doesn't have CX. This also mirrors the previous definition so no code change is required. Also add TRFCR_EL12 which will start to be used in a later commit. Unfortunately, to avoid breaking the Perf build with duplicate definition errors, the tools copy of the sysreg.h header needs to be updated at the same time rather than the usual second commit. This is because the generated version of sysreg (arch/arm64/include/generated/asm/sysreg-defs.h), is currently shared and tools/ does not have its own copy. Signed-off-by: James Clark <james.clark@arm.com> --- arch/arm64/include/asm/sysreg.h | 12 -------- arch/arm64/tools/sysreg | 41 +++++++++++++++++++++++++++ tools/arch/arm64/include/asm/sysreg.h | 12 -------- 3 files changed, 41 insertions(+), 24 deletions(-)