Message ID | 20240222035158.195265-1-dharma.b@microchip.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v3] dt-bindings: interrupt-controller: Convert Atmel AIC to json-schema | expand |
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml > new file mode 100644 > index 000000000000..0d51bd78bf2b > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml > @@ -0,0 +1,89 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Advanced Interrupt Controller (AIC) > + > +maintainers: > + - Nicolas Ferre <nicolas.ferre@microchip.com> > + - Dharma balasubiramani <dharma.b@microchip.com> > + > +description: > + The Advanced Interrupt Controller (AIC) is an 8-level priority, individually > + maskable, vectored interrupt controller providing handling of up to one > + hundred and twenty-eight interrupt sources. > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + - if: > + properties: > + compatible: > + contains: > + const: atmel,at91rm9200-aic > + then: > + properties: > + atmel,external-irqs: > + minItems: 1 > + maxItems: 7 > + else: > + properties: > + atmel,external-irqs: > + minItems: 1 > + maxItems: 1 When there's property restrictions being applied, move the allof down to... > + > +properties: > + compatible: > + enum: > + - atmel,at91rm9200-aic > + - atmel,sama5d2-aic > + - atmel,sama5d3-aic > + - atmel,sama5d4-aic > + - microchip,sam9x60-aic > + > + reg: > + maxItems: 1 > + > + interrupt-controller: true > + > + "#interrupt-cells": > + const: 3 > + description: | > + The 1st cell is the IRQ number (Peripheral IDentifier on datasheet). > + The 2nd cell specifies flags: > + bits[3:0] trigger type and level flags: > + 1 = low-to-high edge triggered. > + 2 = high-to-low edge triggered. > + 4 = active high level-sensitive. > + 8 = active low level-sensitive. > + Valid combinations: 1, 2, 3, 4, 8. > + Default for internal sources: 4 (active high). > + The 3rd cell specifies irq priority from 0 (lowest) to 7 (highest). > + > + interrupts: > + maxItems: 1 > + > + atmel,external-irqs: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + description: u32 array of external irqs. ...here. Both work, but seeing the restrictions before you see any of the properties is not the most understandable. Cheers, Conor. > +required: > + - compatible > + - reg > + - interrupt-controller > + - "#interrupt-cells" > + - atmel,external-irqs > + > +unevaluatedProperties: false > + > +examples: > + - | > + interrupt-controller@fffff000 { > + compatible = "atmel,at91rm9200-aic"; > + reg = <0xfffff000 0x200>; > + interrupt-controller; > + #interrupt-cells = <3>; > + atmel,external-irqs = <31>; > + }; > +... > > base-commit: 4f5e5092fdbf5cec6bedc19fbe69cce4f5f08372 > -- > 2.25.1 >
On 22/02/24 2:26 pm, Conor Dooley wrote: >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml >> new file mode 100644 >> index 000000000000..0d51bd78bf2b >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml >> @@ -0,0 +1,89 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id:http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml# >> +$schema:http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Advanced Interrupt Controller (AIC) >> + >> +maintainers: >> + - Nicolas Ferre<nicolas.ferre@microchip.com> >> + - Dharma balasubiramani<dharma.b@microchip.com> >> + >> +description: >> + The Advanced Interrupt Controller (AIC) is an 8-level priority, individually >> + maskable, vectored interrupt controller providing handling of up to one >> + hundred and twenty-eight interrupt sources. >> + >> +allOf: >> + - $ref: /schemas/interrupt-controller.yaml# >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: atmel,at91rm9200-aic >> + then: >> + properties: >> + atmel,external-irqs: >> + minItems: 1 >> + maxItems: 7 >> + else: >> + properties: >> + atmel,external-irqs: >> + minItems: 1 >> + maxItems: 1 > When there's property restrictions being applied, move the allof down > to... > >> + >> +properties: >> + compatible: >> + enum: >> + - atmel,at91rm9200-aic >> + - atmel,sama5d2-aic >> + - atmel,sama5d3-aic >> + - atmel,sama5d4-aic >> + - microchip,sam9x60-aic >> + >> + reg: >> + maxItems: 1 >> + >> + interrupt-controller: true >> + >> + "#interrupt-cells": >> + const: 3 >> + description: | >> + The 1st cell is the IRQ number (Peripheral IDentifier on datasheet). >> + The 2nd cell specifies flags: >> + bits[3:0] trigger type and level flags: >> + 1 = low-to-high edge triggered. >> + 2 = high-to-low edge triggered. >> + 4 = active high level-sensitive. >> + 8 = active low level-sensitive. >> + Valid combinations: 1, 2, 3, 4, 8. >> + Default for internal sources: 4 (active high). >> + The 3rd cell specifies irq priority from 0 (lowest) to 7 (highest). >> + >> + interrupts: >> + maxItems: 1 >> + >> + atmel,external-irqs: >> + $ref: /schemas/types.yaml#/definitions/uint32-array >> + description: u32 array of external irqs. > ...here. Both work, but seeing the restrictions before you see any of > the properties is not the most understandable. Understood, I will move it here. > > Cheers, > Conor. > >> +required: >> + - compatible >> + - reg >> + - interrupt-controller >> + - "#interrupt-cells" >> + - atmel,external-irqs >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + interrupt-controller@fffff000 { >> + compatible = "atmel,at91rm9200-aic"; >> + reg = <0xfffff000 0x200>; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + atmel,external-irqs = <31>; >> + }; >> +... >> >> base-commit: 4f5e5092fdbf5cec6bedc19fbe69cce4f5f08372 >> -- >> 2.25.1
diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt deleted file mode 100644 index 7079d44bf3ba..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Advanced Interrupt Controller (AIC) - -Required properties: -- compatible: Should be: - - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2", - "sama5d3" or "sama5d4" - - "microchip,<chip>-aic" where <chip> can be "sam9x60" - -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: The number of cells to define the interrupts. It should be 3. - The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet). - The second cell is used to specify flags: - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - Valid combinations are 1, 2, 3, 4, 8. - Default flag for internal sources should be set to 4 (active high). - The third cell is used to specify the irq priority from 0 (lowest) to 7 - (highest). -- reg: Should contain AIC registers location and length -- atmel,external-irqs: u32 array of external irqs. - -Examples: - /* - * AIC - */ - aic: interrupt-controller@fffff000 { - compatible = "atmel,at91rm9200-aic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xfffff000 0x200>; - }; - - /* - * An interrupt generating device that is wired to an AIC. - */ - dma: dma-controller@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <21 4 5>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml new file mode 100644 index 000000000000..0d51bd78bf2b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Advanced Interrupt Controller (AIC) + +maintainers: + - Nicolas Ferre <nicolas.ferre@microchip.com> + - Dharma balasubiramani <dharma.b@microchip.com> + +description: + The Advanced Interrupt Controller (AIC) is an 8-level priority, individually + maskable, vectored interrupt controller providing handling of up to one + hundred and twenty-eight interrupt sources. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + - if: + properties: + compatible: + contains: + const: atmel,at91rm9200-aic + then: + properties: + atmel,external-irqs: + minItems: 1 + maxItems: 7 + else: + properties: + atmel,external-irqs: + minItems: 1 + maxItems: 1 + +properties: + compatible: + enum: + - atmel,at91rm9200-aic + - atmel,sama5d2-aic + - atmel,sama5d3-aic + - atmel,sama5d4-aic + - microchip,sam9x60-aic + + reg: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 3 + description: | + The 1st cell is the IRQ number (Peripheral IDentifier on datasheet). + The 2nd cell specifies flags: + bits[3:0] trigger type and level flags: + 1 = low-to-high edge triggered. + 2 = high-to-low edge triggered. + 4 = active high level-sensitive. + 8 = active low level-sensitive. + Valid combinations: 1, 2, 3, 4, 8. + Default for internal sources: 4 (active high). + The 3rd cell specifies irq priority from 0 (lowest) to 7 (highest). + + interrupts: + maxItems: 1 + + atmel,external-irqs: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: u32 array of external irqs. + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - atmel,external-irqs + +unevaluatedProperties: false + +examples: + - | + interrupt-controller@fffff000 { + compatible = "atmel,at91rm9200-aic"; + reg = <0xfffff000 0x200>; + interrupt-controller; + #interrupt-cells = <3>; + atmel,external-irqs = <31>; + }; +...