Message ID | 20240223-saradcv2-chan-mask-v1-1-84b06a0f623a@theobroma-systems.com (mailing list archive) |
---|---|
State | Accepted |
Headers | show |
Series | iio: adc: rockchip_saradc: fix bitmasking and remove custom logic for getting reset | expand |
Am Freitag, 23. Februar 2024, 13:45:21 CET schrieb Quentin Schulz: > From: Quentin Schulz <quentin.schulz@theobroma-systems.com> > > The SARADCv2 on RK3588 (the only SoC currently supported that has an > SARADCv2) selects the channel through the channel_sel bitfield which is > the 4 lowest bits, therefore the mask should be GENMASK(3, 0) and not > GENMASK(15, 0). > > Fixes: 757953f8ec69 ("iio: adc: rockchip_saradc: Add support for RK3588") > Cc: Quentin Schulz <foss+kernel@0leil.net> > Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> after checking against the TRM Reviewed-by: Heiko Stuebner <heiko@sntech.de>
diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c index dd94667a623b..2da8d6f3241a 100644 --- a/drivers/iio/adc/rockchip_saradc.c +++ b/drivers/iio/adc/rockchip_saradc.c @@ -52,7 +52,7 @@ #define SARADC2_START BIT(4) #define SARADC2_SINGLE_MODE BIT(5) -#define SARADC2_CONV_CHANNELS GENMASK(15, 0) +#define SARADC2_CONV_CHANNELS GENMASK(3, 0) struct rockchip_saradc;