| Message ID | 20240226-dw-hdma-v3-4-cfcb8171fc24@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | PCI: dwc: Add support for integrating HDMA with DWC EP driver | expand |
On Mon, Feb 26, 2024 at 05:07:29PM +0530, Manivannan Sadhasivam wrote: > From: Mrinmay Sarkar <quic_msarkar@quicinc.com> > > SA8775P SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP. > Let's add support for it by passing the mapping format and the number of > read/write channels count. > > The PCIe EP controller used on this SoC is of version 1.34.0, so a separate > config struct is introduced for the sake of enabling HDMA conditionally. > > It should be noted that for the eDMA support (predecessor of HDMA), there > are no mapping format and channels count specified. That is because eDMA > supports auto detection of both parameters, whereas HDMA doesn't. > > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> > [mani: Reworded commit message, added kdoc, and minor cleanups] > Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom-ep.c | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c > index 45008e054e31..89d06a3e6e06 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c > @@ -149,6 +149,14 @@ enum qcom_pcie_ep_link_status { > QCOM_PCIE_EP_LINK_DOWN, > }; > > +/** > + * struct qcom_pcie_ep_cfg - Per SoC config struct > + * @hdma_support: HDMA support on this SoC > + */ > +struct qcom_pcie_ep_cfg { > + bool hdma_support; > +}; > + > /** > * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller > * @pci: Designware PCIe controller struct > @@ -803,6 +811,7 @@ static const struct dw_pcie_ep_ops pci_ep_ops = { > > static int qcom_pcie_ep_probe(struct platform_device *pdev) > { > + const struct qcom_pcie_ep_cfg *cfg; > struct device *dev = &pdev->dev; > struct qcom_pcie_ep *pcie_ep; > char *name; > @@ -816,6 +825,14 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) > pcie_ep->pci.ops = &pci_ops; > pcie_ep->pci.ep.ops = &pci_ep_ops; > pcie_ep->pci.edma.nr_irqs = 1; > + > + cfg = of_device_get_match_data(dev); > + if (cfg && cfg->hdma_support) { > + pcie_ep->pci.edma.ll_wr_cnt = 8; > + pcie_ep->pci.edma.ll_rd_cnt = 8; > + pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE; > + } > + > platform_set_drvdata(pdev, pcie_ep); > > ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); > @@ -874,8 +891,12 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev) > qcom_pcie_disable_resources(pcie_ep); > } > > +static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { > + .hdma_support = true, > +}; > + > static const struct of_device_id qcom_pcie_ep_match[] = { > - { .compatible = "qcom,sa8775p-pcie-ep", }, > + { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, > { .compatible = "qcom,sdx55-pcie-ep", }, > { .compatible = "qcom,sm8450-pcie-ep", }, > { } > > -- > 2.25.1 >
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 45008e054e31..89d06a3e6e06 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -149,6 +149,14 @@ enum qcom_pcie_ep_link_status { QCOM_PCIE_EP_LINK_DOWN, }; +/** + * struct qcom_pcie_ep_cfg - Per SoC config struct + * @hdma_support: HDMA support on this SoC + */ +struct qcom_pcie_ep_cfg { + bool hdma_support; +}; + /** * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller * @pci: Designware PCIe controller struct @@ -803,6 +811,7 @@ static const struct dw_pcie_ep_ops pci_ep_ops = { static int qcom_pcie_ep_probe(struct platform_device *pdev) { + const struct qcom_pcie_ep_cfg *cfg; struct device *dev = &pdev->dev; struct qcom_pcie_ep *pcie_ep; char *name; @@ -816,6 +825,14 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) pcie_ep->pci.ops = &pci_ops; pcie_ep->pci.ep.ops = &pci_ep_ops; pcie_ep->pci.edma.nr_irqs = 1; + + cfg = of_device_get_match_data(dev); + if (cfg && cfg->hdma_support) { + pcie_ep->pci.edma.ll_wr_cnt = 8; + pcie_ep->pci.edma.ll_rd_cnt = 8; + pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE; + } + platform_set_drvdata(pdev, pcie_ep); ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); @@ -874,8 +891,12 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev) qcom_pcie_disable_resources(pcie_ep); } +static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { + .hdma_support = true, +}; + static const struct of_device_id qcom_pcie_ep_match[] = { - { .compatible = "qcom,sa8775p-pcie-ep", }, + { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, { .compatible = "qcom,sdx55-pcie-ep", }, { .compatible = "qcom,sm8450-pcie-ep", }, { }