diff mbox series

drm/i915: Reuse rplu cdclk fns for mtl/lnl

Message ID 20240226213018.592290-1-radhakrishna.sripada@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Reuse rplu cdclk fns for mtl/lnl | expand

Commit Message

Sripada, Radhakrishna Feb. 26, 2024, 9:30 p.m. UTC
MTL/LNL use the same cdclk functions as rplu albeit with different
tables. Having separate tables not explicit special handling for the
platforms reuse rplu cdclk functions.

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

Comments

Jani Nikula Feb. 27, 2024, 8:50 a.m. UTC | #1
Subject: drm/i915/cdclk: Re-use RPL-U functions for MTL+

On Mon, 26 Feb 2024, Radhakrishna Sripada <radhakrishna.sripada@intel.com> wrote:
> MTL/LNL use the same cdclk functions as rplu albeit with different
> tables. Having separate tables not explicit special handling for the
> platforms reuse rplu cdclk functions.

I'm unable to parse the last sentence.

s/rplu/RPL-U/g

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 11 ++---------
>  1 file changed, 2 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ed89b86ea625..6d2d32f7890d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3534,13 +3534,6 @@ void intel_cdclk_debugfs_register(struct drm_i915_private *i915)
>  			    i915, &i915_cdclk_info_fops);
>  }
>  
> -static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
> -	.get_cdclk = bxt_get_cdclk,
> -	.set_cdclk = bxt_set_cdclk,
> -	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> -	.calc_voltage_level = rplu_calc_voltage_level,
> -};
> -
>  static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
>  	.get_cdclk = bxt_get_cdclk,
>  	.set_cdclk = bxt_set_cdclk,
> @@ -3684,10 +3677,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (DISPLAY_VER(dev_priv) >= 20) {
> -		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> +		dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
>  		dev_priv->display.cdclk.table = lnl_cdclk_table;
>  	} else if (DISPLAY_VER(dev_priv) >= 14) {
> -		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> +		dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
>  		dev_priv->display.cdclk.table = mtl_cdclk_table;
>  	} else if (IS_DG2(dev_priv)) {
>  		dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ed89b86ea625..6d2d32f7890d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3534,13 +3534,6 @@  void intel_cdclk_debugfs_register(struct drm_i915_private *i915)
 			    i915, &i915_cdclk_info_fops);
 }
 
-static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
-	.get_cdclk = bxt_get_cdclk,
-	.set_cdclk = bxt_set_cdclk,
-	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
-	.calc_voltage_level = rplu_calc_voltage_level,
-};
-
 static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
 	.get_cdclk = bxt_get_cdclk,
 	.set_cdclk = bxt_set_cdclk,
@@ -3684,10 +3677,10 @@  static const struct intel_cdclk_funcs i830_cdclk_funcs = {
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
 	if (DISPLAY_VER(dev_priv) >= 20) {
-		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+		dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
 		dev_priv->display.cdclk.table = lnl_cdclk_table;
 	} else if (DISPLAY_VER(dev_priv) >= 14) {
-		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+		dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
 		dev_priv->display.cdclk.table = mtl_cdclk_table;
 	} else if (IS_DG2(dev_priv)) {
 		dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;