| Message ID | 20240205171930.968-3-linux.amoon@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [PATCHv1,1/5] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC | expand |
On 05/02/2024 18:19, Anand Moon wrote: > As per S905X3 datasheet add missing cache information to the Amlogic > SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache. > > - Each Cortex-A55 core has 32KB of L1 instruction cache available and > 32KB of L1 data cache available. > - Along with 512KB Unified L3 cache. This 512K number is for the NPU, AFAIK the CPU L3 Cache size isn't specified in the datasheet > > To improve system performance. > > Signed-off-by: Anand Moon <linux.amoon@gmail.com> > --- > Datasheet > [0] https://dn.odroid.com/S905X3/ODROID-C4/Docs/S905X3_Public_Datasheet_Hardkernel.pdf > [1] https://en.wikipedia.org/wiki/ARM_Cortex-A55 > --- > arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 39 ++++++++++++++++++---- > 1 file changed, 33 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi > index 643f94d9d08e..403443e782e4 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi > @@ -55,7 +55,13 @@ cpu0: cpu@0 { > compatible = "arm,cortex-a55"; > reg = <0x0 0x0>; > enable-method = "psci"; > - next-level-cache = <&l2>; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l3>; > #cooling-cells = <2>; > }; > > @@ -64,7 +70,13 @@ cpu1: cpu@1 { > compatible = "arm,cortex-a55"; > reg = <0x0 0x1>; > enable-method = "psci"; > - next-level-cache = <&l2>; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l3>; > #cooling-cells = <2>; > }; > > @@ -73,7 +85,13 @@ cpu2: cpu@2 { > compatible = "arm,cortex-a55"; > reg = <0x0 0x2>; > enable-method = "psci"; > - next-level-cache = <&l2>; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l3>; > #cooling-cells = <2>; > }; > > @@ -82,14 +100,23 @@ cpu3: cpu@3 { > compatible = "arm,cortex-a55"; > reg = <0x0 0x3>; > enable-method = "psci"; > - next-level-cache = <&l2>; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l3>; > #cooling-cells = <2>; > }; > > - l2: l2-cache0 { > + l3: l3-cache0 { > compatible = "cache"; > - cache-level = <2>; > + cache-level = <3>; > cache-unified; > + cache-size = <0x7d000>; /* L2. 512 KB */ Comment should be L3 here > + cache-line-size = <64>; > + cache-sets = <512>; > }; > }; > Thanks, Neil
Hi Neil, On Tue, 6 Feb 2024 at 14:24, Neil Armstrong <neil.armstrong@linaro.org> wrote: > > On 05/02/2024 18:19, Anand Moon wrote: > > As per S905X3 datasheet add missing cache information to the Amlogic > > SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache. > > > > - Each Cortex-A55 core has 32KB of L1 instruction cache available and > > 32KB of L1 data cache available. > > - Along with 512KB Unified L3 cache. > > This 512K number is for the NPU, AFAIK the CPU L3 Cache size isn't specified in the datasheet > OK, As per Arm Cotex A55 TRM it supports cache. [0] https://developer.arm.com/documentation/100442/0200/Functional-description/Introduction-to-the-Cortex-A55-core/Implementation-options As per the datasheet [1] https://dn.odroid.com/S905X3/ODROID-C4/Docs/S905X3_Public_Datasheet_Hardkernel.pdf TheCortex™-A55M subsystem of the chipisa high-performance, low-power,ARM macro cell with an L1 and L3 cache sub system that provide full virtual memory capabilities. Best way to let the Amlogic SoC members comment on the CPU L1/ //L2/ L3 cache size. But with the lack of pref PMU events we cannot test this feature. [root@odroid-c4 alarm]# perf list List of pre-defined events (to be used in -e or -M): alignment-faults [Software event] bpf-output [Software event] cgroup-switches [Software event] context-switches OR cs [Software event] List of pre-defined events (to be used in -e or -M): alignment-faults [Software event] bpf-output [Software event] cgroup-switches [Software event] context-switches OR cs [Software event] cpu-clock [Software event] cpu-migrations OR migrations [Software event] dummy [Software event] emulation-faults [Software event] major-faults [Software event] minor-faults [Software event] page-faults OR faults [Software event] task-clock [Software event] duration_time [Tool event] user_time [Tool event] system_time [Tool event] rNNN [Raw hardware event descri> cpu/t1=v1[,t2=v2,t3 ...]/modifier [Raw hardware event descri> [(see 'man perf-list' on how to encode it)] mem:<addr>[/len][:access] [Hardware breakpoint] alarmtimer:alarmtimer_cancel [Tracepoint event] alarmtimer:alarmtimer_fired [Tracepoint event] alarmtimer:alarmtimer_start [Tracepoint event] alarmtimer:alarmtimer_suspend [Tracepoint event] asoc:snd_soc_bias_level_done [Tracepoint event] asoc:snd_soc_bias_level_start [Tracepoint event] asoc:snd_soc_dapm_connected [Tracepoint event] asoc:snd_soc_dapm_done [Tracepoint event] asoc:snd_soc_dapm_path [Tracepoint event] asoc:snd_soc_dapm_start [Tracepoint event] asoc:snd_soc_dapm_walk_done [Tracepoint event] asoc:snd_soc_dapm_widget_event_done [Tracepoint event] asoc:snd_soc_dapm_widget_event_start [Tracepoint event] asoc:snd_soc_dapm_widget_power [Tracepoint event] Thanks -Anand
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 643f94d9d08e..403443e782e4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -55,7 +55,13 @@ cpu0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0x0 0x0>; enable-method = "psci"; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l3>; #cooling-cells = <2>; }; @@ -64,7 +70,13 @@ cpu1: cpu@1 { compatible = "arm,cortex-a55"; reg = <0x0 0x1>; enable-method = "psci"; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l3>; #cooling-cells = <2>; }; @@ -73,7 +85,13 @@ cpu2: cpu@2 { compatible = "arm,cortex-a55"; reg = <0x0 0x2>; enable-method = "psci"; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l3>; #cooling-cells = <2>; }; @@ -82,14 +100,23 @@ cpu3: cpu@3 { compatible = "arm,cortex-a55"; reg = <0x0 0x3>; enable-method = "psci"; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l3>; #cooling-cells = <2>; }; - l2: l2-cache0 { + l3: l3-cache0 { compatible = "cache"; - cache-level = <2>; + cache-level = <3>; cache-unified; + cache-size = <0x7d000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; };
As per S905X3 datasheet add missing cache information to the Amlogic SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache. - Each Cortex-A55 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L3 cache. To improve system performance. Signed-off-by: Anand Moon <linux.amoon@gmail.com> --- Datasheet [0] https://dn.odroid.com/S905X3/ODROID-C4/Docs/S905X3_Public_Datasheet_Hardkernel.pdf [1] https://en.wikipedia.org/wiki/ARM_Cortex-A55 --- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 39 ++++++++++++++++++---- 1 file changed, 33 insertions(+), 6 deletions(-)